Message ID | 20230825081328.204442-5-william.qiu@starfivetech.com |
---|---|
State | New |
Headers | show |
Series | StarFive's Pulse Width Modulation driver support | expand |
On Fri, 25 Aug 2023 16:13:28 +0800, William Qiu wrote: > Add StarFive JH7100 PWM controller node and add PWM pins configuration > on VisionFive 2 board. > > Signed-off-by: William Qiu <william.qiu@starfivetech.com> Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
On Fri, 25 Aug 2023 at 10:16, William Qiu <william.qiu@starfivetech.com> wrote: > Add StarFive JH7100 PWM controller node and add PWM pins configuration > on VisionFive 2 board. Hi William, This is the VisionFive V1 board right? /Emil > Signed-off-by: William Qiu <william.qiu@starfivetech.com> > --- > .../boot/dts/starfive/jh7100-common.dtsi | 24 +++++++++++++++++++ > arch/riscv/boot/dts/starfive/jh7100.dtsi | 9 +++++++ > 2 files changed, 33 insertions(+) > > diff --git a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi > index b93ce351a90f..746867b882b0 100644 > --- a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi > @@ -84,6 +84,24 @@ GPO_I2C2_PAD_SDA_OEN, > }; > }; > > + pwm_pins: pwm-0 { > + pwm-pins { > + pinmux = <GPIOMUX(7, > + GPO_PWM_PAD_OUT_BIT0, > + GPO_PWM_PAD_OE_N_BIT0, > + GPI_NONE)>, > + <GPIOMUX(5, > + GPO_PWM_PAD_OUT_BIT1, > + GPO_PWM_PAD_OE_N_BIT1, > + GPI_NONE)>; > + bias-disable; > + drive-strength = <35>; > + input-disable; > + input-schmitt-disable; > + slew-rate = <0>; > + }; > + }; > + > uart3_pins: uart3-0 { > rx-pins { > pinmux = <GPIOMUX(13, GPO_LOW, GPO_DISABLE, > @@ -154,6 +172,12 @@ &osc_aud { > clock-frequency = <27000000>; > }; > > +&ptc { > + pinctrl-names = "default"; > + pinctrl-0 = <&pwm_pins>; > + status = "okay"; > +}; > + > &uart3 { > pinctrl-names = "default"; > pinctrl-0 = <&uart3_pins>; > diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi > index 4218621ea3b9..7f5bb19e636e 100644 > --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi > @@ -248,5 +248,14 @@ watchdog@12480000 { > resets = <&rstgen JH7100_RSTN_WDTIMER_APB>, > <&rstgen JH7100_RSTN_WDT>; > }; > + > + ptc: pwm@12490000 { > + compatible = "starfive,jh7100-pwm"; > + reg = <0x0 0x12490000 0x0 0x10000>; > + clocks = <&clkgen JH7100_CLK_PWM_APB>; > + resets = <&rstgen JH7100_RSTN_PWM_APB>; > + #pwm-cells = <3>; > + status = "disabled"; > + }; > }; > }; > -- > 2.34.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
diff --git a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi index b93ce351a90f..746867b882b0 100644 --- a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi @@ -84,6 +84,24 @@ GPO_I2C2_PAD_SDA_OEN, }; }; + pwm_pins: pwm-0 { + pwm-pins { + pinmux = <GPIOMUX(7, + GPO_PWM_PAD_OUT_BIT0, + GPO_PWM_PAD_OE_N_BIT0, + GPI_NONE)>, + <GPIOMUX(5, + GPO_PWM_PAD_OUT_BIT1, + GPO_PWM_PAD_OE_N_BIT1, + GPI_NONE)>; + bias-disable; + drive-strength = <35>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; + uart3_pins: uart3-0 { rx-pins { pinmux = <GPIOMUX(13, GPO_LOW, GPO_DISABLE, @@ -154,6 +172,12 @@ &osc_aud { clock-frequency = <27000000>; }; +&ptc { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; + status = "okay"; +}; + &uart3 { pinctrl-names = "default"; pinctrl-0 = <&uart3_pins>; diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index 4218621ea3b9..7f5bb19e636e 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -248,5 +248,14 @@ watchdog@12480000 { resets = <&rstgen JH7100_RSTN_WDTIMER_APB>, <&rstgen JH7100_RSTN_WDT>; }; + + ptc: pwm@12490000 { + compatible = "starfive,jh7100-pwm"; + reg = <0x0 0x12490000 0x0 0x10000>; + clocks = <&clkgen JH7100_CLK_PWM_APB>; + resets = <&rstgen JH7100_RSTN_PWM_APB>; + #pwm-cells = <3>; + status = "disabled"; + }; }; };
Add StarFive JH7100 PWM controller node and add PWM pins configuration on VisionFive 2 board. Signed-off-by: William Qiu <william.qiu@starfivetech.com> --- .../boot/dts/starfive/jh7100-common.dtsi | 24 +++++++++++++++++++ arch/riscv/boot/dts/starfive/jh7100.dtsi | 9 +++++++ 2 files changed, 33 insertions(+) -- 2.34.1