From patchwork Fri Aug 25 08:13:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Qiu X-Patchwork-Id: 717022 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9C926C7EE2C for ; Fri, 25 Aug 2023 08:15:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232202AbjHYIOl convert rfc822-to-8bit (ORCPT ); Fri, 25 Aug 2023 04:14:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42562 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243502AbjHYIOR (ORCPT ); Fri, 25 Aug 2023 04:14:17 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 181252693; Fri, 25 Aug 2023 01:13:46 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id CCAFB81F6; Fri, 25 Aug 2023 16:13:30 +0800 (CST) Received: from EXMBX168.cuchost.com (172.16.6.78) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 25 Aug 2023 16:13:30 +0800 Received: from williamqiu-virtual-machine.starfivetech.com (171.223.208.138) by EXMBX168.cuchost.com (172.16.6.78) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 25 Aug 2023 16:13:29 +0800 From: William Qiu To: , , , CC: Emil Renner Berthing , Rob Herring , Philipp Zabel , Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Krzysztof Kozlowski , Conor Dooley , "Paul Walmsley" , Palmer Dabbelt , Albert Ou , Hal Feng , William Qiu Subject: [RFC v4 1/4] dt-bindings: pwm: Add StarFive PWM module Date: Fri, 25 Aug 2023 16:13:25 +0800 Message-ID: <20230825081328.204442-2-william.qiu@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230825081328.204442-1-william.qiu@starfivetech.com> References: <20230825081328.204442-1-william.qiu@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX168.cuchost.com (172.16.6.78) X-YovoleRuleAgent: yovoleflag Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add documentation to describe StarFive Pulse Width Modulation controller driver. Signed-off-by: William Qiu Reviewed-by: Krzysztof Kozlowski Reviewed-by: Hal Feng --- .../bindings/pwm/starfive,jh7100-pwm.yaml | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/starfive,jh7100-pwm.yaml -- 2.34.1 diff --git a/Documentation/devicetree/bindings/pwm/starfive,jh7100-pwm.yaml b/Documentation/devicetree/bindings/pwm/starfive,jh7100-pwm.yaml new file mode 100644 index 000000000000..6f1937beb962 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/starfive,jh7100-pwm.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/starfive,jh7100-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7100 and JH7110 PWM controller + +maintainers: + - William Qiu + +description: + StarFive SoCs contain PWM and when operating in PWM mode, the PTC core generates + binary signal with user-programmable low and high periods. Clock source for the + PWM can be either system clock or external clock. Each PWM timer block provides 8 + PWM channels. + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + enum: + - starfive,jh7100-pwm + - starfive,jh7110-pwm + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + "#pwm-cells": + const: 3 + +required: + - compatible + - reg + - clocks + - resets + +additionalProperties: false + +examples: + - | + pwm@12490000 { + compatible = "starfive,jh7100-pwm"; + reg = <0x12490000 0x10000>; + clocks = <&clkgen 181>; + resets = <&rstgen 109>; + #pwm-cells = <3>; + };