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Tue, 22 Aug 2023 15:53:59 +0000 From: Frank Li To: frank.li@nxp.com, shawnguo@kernel.org, joy.zou@nxp.com, shenwei.wang@nxp.com, sherry.sun@nxp.com Cc: clin@suse.com, conor+dt@kernel.org, devicetree@vger.kernel.org, eagle.zhou@nxp.com, festevam@gmail.com, imx@lists.linux.dev, kernel@pengutronix.de, krzysztof.kozlowski+dt@linaro.org, leoyang.li@nxp.com, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-kernel@vger.kernel.org, pierre.gondois@arm.com, robh+dt@kernel.org, s.hauer@pengutronix.de Subject: [PATCH 1/5] firmware: imx: scu-pd: added missing edma channel power domain Date: Tue, 22 Aug 2023 11:53:29 -0400 Message-Id: <20230822155333.2261262-2-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230822155333.2261262-1-Frank.Li@nxp.com> References: <20230822155333.2261262-1-Frank.Li@nxp.com> X-ClientProxiedBy: SJ0PR03CA0231.namprd03.prod.outlook.com (2603:10b6:a03:39f::26) To AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB4838:EE_|PR3PR04MB7322:EE_ X-MS-Office365-Filtering-Correlation-Id: 11d20e2a-fec5-4d46-f97f-08dba327ff52 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Signed-off-by: Frank Li --- drivers/firmware/imx/scu-pd.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/firmware/imx/scu-pd.c b/drivers/firmware/imx/scu-pd.c index 84b673427073..7d80eabd7941 100644 --- a/drivers/firmware/imx/scu-pd.c +++ b/drivers/firmware/imx/scu-pd.c @@ -121,9 +121,11 @@ static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = { { "audio-pll1", IMX_SC_R_AUDIO_PLL_1, 1, false, 0 }, { "audio-clk-0", IMX_SC_R_AUDIO_CLK_0, 1, false, 0 }, { "audio-clk-1", IMX_SC_R_AUDIO_CLK_1, 1, false, 0 }, - { "dma0-ch", IMX_SC_R_DMA_0_CH0, 16, true, 0 }, + { "dma0-ch", IMX_SC_R_DMA_0_CH0, 32, true, 0 }, { "dma1-ch", IMX_SC_R_DMA_1_CH0, 16, true, 0 }, - { "dma2-ch", IMX_SC_R_DMA_2_CH0, 5, true, 0 }, + { "dma2-ch-0", IMX_SC_R_DMA_2_CH0, 5, true, 0 }, + { "dma2-ch-1", IMX_SC_R_DMA_2_CH5, 27, true, 0 }, + { "dma3-ch", IMX_SC_R_DMA_3_CH0, 32, true, 0 }, { "asrc0", IMX_SC_R_ASRC_0, 1, false, 0 }, { "asrc1", IMX_SC_R_ASRC_1, 1, false, 0 }, { "esai0", IMX_SC_R_ESAI_0, 1, false, 0 },