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Date: Mon, 14 Aug 2023 22:44:05 +0530 Message-ID: <20230814171406.214932-4-thippeswamy.havalige@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230814171406.214932-1-thippeswamy.havalige@amd.com> References: <20230814171406.214932-1-thippeswamy.havalige@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D3:EE_|PH7PR12MB5733:EE_ X-MS-Office365-Filtering-Correlation-Id: 49712f60-c32e-46eb-0071-08db9cea09c9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: HwGanJwkHWp6AIigJhwHnCy4b7yL10y1p7J0D92ZaBppAShzuyEellpOeylejbpogySFp43Px1lRjlYiskRUQ/WhHGInAzQ1n3MeBXNsTJhHc1Xm/suSD1cv/XRBasC+s8uRxkTP3R4PNz8Z6o8aFzeID9PL9LuZMlk15h5YedT/U9qFK/j0V3D1gtAjj7ZwWC0zVAVST2UwbjadFFhmzi5kJWraCu4vyY5xwu2Vfu9PSlPTo3+rnWQsgVJXAghcV/l6W7E1VaytEkYCcN6VvpuA42UkZK5u4pkbWWps3nvJhwq8l7K+qWBfXXjzY07FYbYomATKPtJmTjxyloOaAGVtMqlxjxA8c9Uf7pcuQyjIJtngCu32hbQ6aq9OUxGLEQsrGQeseWdE+6Nn7B+p/t5KfLSRx1/D0VpgkHE/Hc2qYhvIRuvLlYMyxaSvnwcZn+UhWdeGsKfua51GRKLZU5982rvNZc/GZOIjss2pOw/O2AeHnrx3igor+Z0BK+cyrkq9p64Ut6iCVwnUMSze9tdURYdEEV8y9F9E8Al3sQubt2kCEVSSN5rPV/DsQtg8ZUxaavit3D3Cho51hALGd0MpBNNq83keW7KGQQfU9qG7eYyDV7ntfHQwWwD/qWVM6JFbXlgtSZ84VzwT7yBef7kRGvfTJYexbYVep9Oo6Y3uSo7eC9/TM4Azdrf4/ql/aP44Qebt5D5X7Pg5uF5bJj0qlZYtViO0dO9xXFAuOdtLiVRjkwBlaRIqRx61KcUnuVF/2ujtaWIBkN1J4Ra2sg== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230028)(4636009)(376002)(396003)(136003)(39860400002)(346002)(186006)(1800799006)(82310400008)(451199021)(46966006)(40470700004)(36840700001)(83380400001)(36756003)(426003)(336012)(47076005)(36860700001)(86362001)(40480700001)(41300700001)(478600001)(356005)(81166007)(54906003)(70586007)(70206006)(316002)(8676002)(5660300002)(4326008)(44832011)(82740400003)(8936002)(110136005)(40460700003)(2616005)(1076003)(26005)(2906002)(6666004)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Aug 2023 17:15:20.2567 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 49712f60-c32e-46eb-0071-08db9cea09c9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D3.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5733 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Rename "NWL_ECAM_VALUE_DEFAULT" to a suitable macro name and remove redundant code. Signed-off-by: Thippeswamy Havalige Signed-off-by: Bharat Kumar Gogada --- changes in v4: - Rename macro changes in v3: - Remove periods at end of subject line - Update commit logs changes in v2: - Update this changes in a seperate patch. --- drivers/pci/controller/pcie-xilinx-nwl.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c index d8a3a08be1d5..8fe0e8a325b0 100644 --- a/drivers/pci/controller/pcie-xilinx-nwl.c +++ b/drivers/pci/controller/pcie-xilinx-nwl.c @@ -126,7 +126,7 @@ #define E_ECAM_CR_ENABLE BIT(0) #define E_ECAM_SIZE_LOC GENMASK(20, 16) #define E_ECAM_SIZE_SHIFT 16 -#define NWL_ECAM_VALUE_DEFAULT 12 +#define NWL_ECAM_MAX_SIZE 12 #define CFG_DMA_REG_BAR GENMASK(2, 0) #define CFG_PCIE_CACHE GENMASK(7, 0) @@ -165,7 +165,6 @@ struct nwl_pcie { u32 ecam_size; int irq_intx; int irq_misc; - u32 ecam_value; struct nwl_msi msi; struct irq_domain *legacy_irq_domain; struct clk *clk; @@ -674,7 +673,7 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) E_ECAM_CR_ENABLE, E_ECAM_CONTROL); nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) | - (pcie->ecam_value << E_ECAM_SIZE_SHIFT), + (NWL_ECAM_MAX_SIZE << E_ECAM_SIZE_SHIFT), E_ECAM_CONTROL); nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base), @@ -782,7 +781,6 @@ static int nwl_pcie_probe(struct platform_device *pdev) pcie = pci_host_bridge_priv(bridge); pcie->dev = dev; - pcie->ecam_value = NWL_ECAM_VALUE_DEFAULT; err = nwl_pcie_parse_dt(pcie, pdev); if (err) {