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Date: Mon, 7 Aug 2023 16:34:36 +0530 Message-ID: <20230807110436.77287-2-thippeswamy.havalige@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230807110436.77287-1-thippeswamy.havalige@amd.com> References: <20230807110436.77287-1-thippeswamy.havalige@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000989EC:EE_|DS0PR12MB6557:EE_ X-MS-Office365-Filtering-Correlation-Id: 240f8c36-8d1d-41b9-2d6a-08db97361d01 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: FP2ZqdJb8mvT1XDgQOCOe6IJ5d44OEiGRlkAOcnyGq8zifn+CYMQmeJF3DPJA10smfi13BVd5Z59Pnj7XbrfmjD8NySopxo+eAXzLMgVrFl+Me8m6dxBDGjJ+ZhZijsnxJlRg4AphH+EMLWganpwRXjnEIehM9Cw1MlZvQNczTYDDLL16ZQtV4RAr2ki3Z6cxyj16ZhIzw3EWpbpEiIkS+yEAx/isKga5C4ruGIv1nZdm2fmTTItDERwufot2XWYc0LF7LqYIJV4JShfQSKwz1wzd7vB/B5S1KUNeYZmEopr1uHiwQUnbYE53o5kYNSOxjOc4mEmPtnetRzPJHY7nFl5XNdR+V4ZZXKE9p/KoCTTcF3SjML3gAexBbqI3RezAyIMMGTfsmMw0GEgrjstSR9QG7+jjQFLuuwLJbh7J1GFDztQfbHKYJRmxt110lzpHkuUCbiNKQoZrvvuGDaa2ELneeXQoOSnwGxugznXAhBrD+zrBSw3hzezRdbk3T0+wIlAfv232v6kQdDQ3oNgZqRqXZBuI+NyeafxrUz4sRwd4Qt6kNGE9qeX2iYhK9JH4LGYoAX0e4tjz7QVdTDa2brCKBxxHLPHNEgYyMMjbYsPvsC2dgvz8f2PiahJnbuQtxDC+q7ueBIAlV5crSVjkO73bhEoSh3VyKGd0c2HV54UTzIAJosyQ1te3Tw1vrQo41TdL079yRHs60WwWeOYi+LgOxJeZZ/kefKiitVg5iiXBGNRqbDOuo9J68zK/Ak9fI9H4JP2Y5UWnZ4tcmzUyw== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230028)(4636009)(136003)(39860400002)(376002)(396003)(346002)(451199021)(82310400008)(1800799003)(186006)(46966006)(40470700004)(36840700001)(40480700001)(2616005)(40460700003)(6666004)(478600001)(86362001)(966005)(82740400003)(81166007)(26005)(36756003)(1076003)(15650500001)(356005)(41300700001)(316002)(8936002)(5660300002)(44832011)(8676002)(54906003)(110136005)(4326008)(2906002)(70586007)(70206006)(336012)(83380400001)(47076005)(36860700001)(426003)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Aug 2023 11:04:47.1982 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 240f8c36-8d1d-41b9-2d6a-08db97361d01 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000989EC.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6557 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Our controller is expecting ECAM size to be programmed by software. By programming "NWL_ECAM_VALUE_DEFAULT 12" controller can access up to 16MB ECAM region which is used to detect 16 buses, so by updating "NWL_ECAM_VALUE_DEFAULT " to 16 so that controller can access up to 256MB ECAM region to detect 256 buses. E_ECAM_CONTROL register from bit 16 to 20 uses this value as input to calculate ECAM Size. The primary,secondary and sub-ordinate bus number registers are updated by Linux PCI core, so removing code which is updating primary,secondary and sub-ordinate bus numbers of type 1 header 18th offset of ECAM. Signed-off-by: Thippeswamy Havalige Signed-off-by: Bharat Kumar Gogada --- | Reported-by: kernel test robot | Closes: | https://lore.kernel.org/oe-kbuild-all/202308040330.eMTjX3tF-lkp@intel. | com/ --- drivers/pci/controller/pcie-xilinx-nwl.c | 18 +++--------------- 1 file changed, 3 insertions(+), 15 deletions(-) diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c index 176686b..b515019 100644 --- a/drivers/pci/controller/pcie-xilinx-nwl.c +++ b/drivers/pci/controller/pcie-xilinx-nwl.c @@ -126,7 +126,7 @@ #define E_ECAM_CR_ENABLE BIT(0) #define E_ECAM_SIZE_LOC GENMASK(20, 16) #define E_ECAM_SIZE_SHIFT 16 -#define NWL_ECAM_VALUE_DEFAULT 12 +#define NWL_ECAM_VALUE_DEFAULT 16 #define CFG_DMA_REG_BAR GENMASK(2, 0) #define CFG_PCIE_CACHE GENMASK(7, 0) @@ -165,8 +165,6 @@ struct nwl_pcie { u32 ecam_size; int irq_intx; int irq_misc; - u32 ecam_value; - u8 last_busno; struct nwl_msi msi; struct irq_domain *legacy_irq_domain; struct clk *clk; @@ -625,7 +623,7 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) { struct device *dev = pcie->dev; struct platform_device *pdev = to_platform_device(dev); - u32 breg_val, ecam_val, first_busno = 0; + u32 breg_val, ecam_val; int err; breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT; @@ -675,7 +673,7 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) E_ECAM_CR_ENABLE, E_ECAM_CONTROL); nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) | - (pcie->ecam_value << E_ECAM_SIZE_SHIFT), + (NWL_ECAM_VALUE_DEFAULT << E_ECAM_SIZE_SHIFT), E_ECAM_CONTROL); nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base), @@ -683,15 +681,6 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base), E_ECAM_BASE_HI); - /* Get bus range */ - ecam_val = nwl_bridge_readl(pcie, E_ECAM_CONTROL); - pcie->last_busno = (ecam_val & E_ECAM_SIZE_LOC) >> E_ECAM_SIZE_SHIFT; - /* Write primary, secondary and subordinate bus numbers */ - ecam_val = first_busno; - ecam_val |= (first_busno + 1) << 8; - ecam_val |= (pcie->last_busno << E_ECAM_SIZE_SHIFT); - writel(ecam_val, (pcie->ecam_base + PCI_PRIMARY_BUS)); - if (nwl_pcie_link_up(pcie)) dev_info(dev, "Link is UP\n"); else @@ -792,7 +781,6 @@ static int nwl_pcie_probe(struct platform_device *pdev) pcie = pci_host_bridge_priv(bridge); pcie->dev = dev; - pcie->ecam_value = NWL_ECAM_VALUE_DEFAULT; err = nwl_pcie_parse_dt(pcie, pdev); if (err) {