From patchwork Fri Jul 21 22:15:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Watts X-Patchwork-Id: 705051 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD025EB64DD for ; Fri, 21 Jul 2023 22:17:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229726AbjGUWRR (ORCPT ); Fri, 21 Jul 2023 18:17:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59734 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229945AbjGUWRQ (ORCPT ); Fri, 21 Jul 2023 18:17:16 -0400 Received: from out-50.mta0.migadu.com (out-50.mta0.migadu.com [91.218.175.50]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E7F7A3A9E for ; Fri, 21 Jul 2023 15:16:55 -0700 (PDT) X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=jookia.org; s=key1; t=1689977814; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=i8V7IVCzXvQ6XGySh6Ck14V+DjdeQUJghLQf/W+Pqwc=; b=0W0U/GT0SbHueJkHt3BR0jUMuIhycCoabty8TdgDcWU1WsD01G4yN21m8enKzd5i7I23Of zq5/9ObfINIDztVU/dkNPuH545rXOAoOEC9qWRJGya925xngV3A2ojquTOGxtuSJ290Z4J Lb6KAIBgWX8LTczvY5PDb1DZsYpgbgOttwKgQRkmLdbzXPAA5SqyQ9OWmEmPdIUuuCCz4h 6ysAK1G9f4VPxgfHPWj20BUXMg+2JhOd1FNzNw/ldyVjRIz24lL3TqI2Y8q8X5jVSXDy5V eO5g6HYTI4UFbvyAEyNoc72MqlfCEtNhCtzXz5PZQT0xv82KFHdz4bH9WPbvkQ== From: John Watts To: linux-sunxi@lists.linux.dev Cc: Wolfgang Grandegger , Marc Kleine-Budde , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-can@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, John Watts Subject: [PATCH v2 2/4] riscv: dts: allwinner: d1: Add CAN controller nodes Date: Sat, 22 Jul 2023 08:15:51 +1000 Message-ID: <20230721221552.1973203-4-contact@jookia.org> In-Reply-To: <20230721221552.1973203-2-contact@jookia.org> References: <20230721221552.1973203-2-contact@jookia.org> MIME-Version: 1.0 X-Migadu-Flow: FLOW_OUT Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Allwinner D1, T113 provide two CAN controllers that are variants of the R40 controller. I have tested support for these controllers on two boards: - A Lichee Panel RV 86 Panel running a D1 chip - A Mango Pi MQ Dual running a T113-s3 chip Both of these fully support both CAN controllers. Signed-off-by: John Watts --- .../boot/dts/allwinner/sunxi-d1s-t113.dtsi | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi index 1bb1e5cae602..4086c0cc0f9d 100644 --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi @@ -131,6 +131,18 @@ uart3_pb_pins: uart3-pb-pins { pins = "PB6", "PB7"; function = "uart3"; }; + + /omit-if-no-ref/ + can0_pins: can0-pins { + pins = "PB2", "PB3"; + function = "can0"; + }; + + /omit-if-no-ref/ + can1_pins: can1-pins { + pins = "PB4", "PB5"; + function = "can1"; + }; }; ccu: clock-controller@2001000 { @@ -879,5 +891,23 @@ rtc: rtc@7090000 { clock-names = "bus", "hosc", "ahb"; #clock-cells = <1>; }; + + can0: can@2504000 { + compatible = "allwinner,sun20i-d1-can"; + reg = <0x02504000 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_CAN0>; + resets = <&ccu RST_BUS_CAN0>; + status = "disabled"; + }; + + can1: can@2504400 { + compatible = "allwinner,sun20i-d1-can"; + reg = <0x02504400 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_CAN1>; + resets = <&ccu RST_BUS_CAN1>; + status = "disabled"; + }; }; };