From patchwork Wed Jul 19 11:35:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 704426 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A96FEB64DA for ; Wed, 19 Jul 2023 11:36:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229659AbjGSLgR (ORCPT ); Wed, 19 Jul 2023 07:36:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53210 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230183AbjGSLgP (ORCPT ); Wed, 19 Jul 2023 07:36:15 -0400 Received: from mail-pf1-x435.google.com (mail-pf1-x435.google.com [IPv6:2607:f8b0:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 786A8173B for ; Wed, 19 Jul 2023 04:36:11 -0700 (PDT) Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-6686c74183cso6768746b3a.1 for ; Wed, 19 Jul 2023 04:36:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1689766570; x=1690371370; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oQiwHLQTp/8j8gItu3f4LCSePQxOFgN8ncFMh196Onk=; b=WAO50NkUFcJNAH38hHesi1r+AhVYkQ3T7HiabLtaPKGo+n8KaN9dQ1BPiWlPZaxre0 ghmIUYzEflFP9s1yN4PmzDbFFZ3yLfhMG/c525rbrL0geQ7j3gmj9QA7MFxracRRnpBX swRP3S5w3ETO+2wgm4HsU9zgSReM4HzTxHPhVJueMsqDmzQB68lzUJSCRdWMCqMX8X/R ESSNoscvZvcfLh3V+F3fWiIh306v+SdhgYkHCByFQf48Ij43zRqR2DU8rKIfB4sm53sL qNGiTx+lgH0c4HPRODh5UqpGjqiqeOtcK8xM3/ADfyHamb9TmsVtx+JvUkIAHYKjWcK+ FK0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689766570; x=1690371370; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oQiwHLQTp/8j8gItu3f4LCSePQxOFgN8ncFMh196Onk=; b=bHKg1Yjj3mv17BbHxkFdtGf6aD41ifxUMNGpHk3POXCC090bu91BWIUc245PX5J+s1 YgsQH71Fzl/u3ucZGjEXGl0FTUKyJi8axeyW/eLvURPHOZBffse7eOF1xqummJIoJEmH Y9C3EfRad9gcxbERDpmVWBwtUv7iqRXqZJgKw4vpaIkpsC3pcRoQJBwkYYVlOpB75jUT bBPxdj+CunpQ0/rn0Mx9VzeKfKChg+gR8XkAv3I7jE2PqF6J2RmRRiQ+KBs5WTQf9JO5 T/f2boJ8uhYyDaLYdm5lzY+SvK5YRPqBhm4dV/0od5GO3mpIdOpeooIMO11pxtrLIfwE ELww== X-Gm-Message-State: ABy/qLZtT506pBF8wWjPR1eZXPA0ImxixytAkGeNldWvjwbsEK65p2KP iGn/vMOf2c67BHVXXnn2s0yhsA== X-Google-Smtp-Source: APBJJlFmLFGryKpfzKpUE3V98g17+lc5UaKu+zvNUvTPMAceFo6f/UbuUr/F/yrJsP0AJyC70N/57w== X-Received: by 2002:a05:6a20:8e10:b0:132:87da:5b57 with SMTP id y16-20020a056a208e1000b0013287da5b57mr22614317pzj.59.1689766570147; Wed, 19 Jul 2023 04:36:10 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([171.76.86.130]) by smtp.gmail.com with ESMTPSA id j10-20020aa783ca000000b00669c99d05fasm3050408pfn.150.2023.07.19.04.36.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Jul 2023 04:36:09 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Frank Rowand , Conor Dooley Cc: Atish Patra , Andrew Jones , Sunil V L , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel Subject: [PATCH v6 03/14] drivers: irqchip/riscv-intc: Mark all INTC nodes as initialized Date: Wed, 19 Jul 2023 17:05:31 +0530 Message-Id: <20230719113542.2293295-4-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230719113542.2293295-1-apatel@ventanamicro.com> References: <20230719113542.2293295-1-apatel@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The RISC-V INTC local interrupts are per-HART (or per-CPU) so we create INTC IRQ domain only for the INTC node belonging to the boot HART. This means only the boot HART INTC node will be marked as initialized and other INTC nodes won't be marked which results downstream interrupt controllers (such as IMSIC and APLIC direct-mode) not being probed due to missing device suppliers. To address this issue, we mark all INTC node for which we don't create IRQ domain as initialized. Signed-off-by: Anup Patel --- drivers/irqchip/irq-riscv-intc.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c index 65f4a2afb381..4e2704bc25fb 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -155,8 +155,16 @@ static int __init riscv_intc_init(struct device_node *node, * for each INTC DT node. We only need to do INTC initialization * for the INTC DT node belonging to boot CPU (or boot HART). */ - if (riscv_hartid_to_cpuid(hartid) != smp_processor_id()) + if (riscv_hartid_to_cpuid(hartid) != smp_processor_id()) { + /* + * The INTC nodes of each CPU are suppliers for downstream + * interrupt controllers (such as IMSIC and APLIC direct-mode) + * so we should mark an INTC node as initialized if we are + * not creating IRQ domain for it. + */ + fwnode_dev_initialized(of_fwnode_handle(node), true); return 0; + } return riscv_intc_init_common(of_node_to_fwnode(node)); }