From patchwork Wed Jul 19 11:35:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 704427 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9843EEB64DA for ; Wed, 19 Jul 2023 11:36:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230133AbjGSLgE (ORCPT ); Wed, 19 Jul 2023 07:36:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52898 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229847AbjGSLgB (ORCPT ); Wed, 19 Jul 2023 07:36:01 -0400 Received: from mail-pf1-x429.google.com (mail-pf1-x429.google.com [IPv6:2607:f8b0:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EB339E69 for ; Wed, 19 Jul 2023 04:35:59 -0700 (PDT) Received: by mail-pf1-x429.google.com with SMTP id d2e1a72fcca58-666e6541c98so6817737b3a.2 for ; Wed, 19 Jul 2023 04:35:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1689766559; x=1690371359; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ex8kAjQsuTgLkE/S9ECXNbIEk2g1m62Eq0yrmysJuO4=; b=oU1ryib5EKzy03oFHfMAIU5HKRsBMF2g0CI74gRDY6b1L0baZEzZAyYqDfvmK/n1KH ZCEat6jNr5YbNK/I77r3eTlGxiUJnCIgk4RBG9tzNUGMhw+DSDM3+G2UlDyuvIIwwKtF WcrgiFxE/fd8Gv5I0AFozy2PyOxMZnb9pm+4cqR/wEpEwcUGyeEXyE73GV8pcB27X+4G mBsOrwcZPG/DwIWGZSucSs3LS3Xed0r20ysGdy6sNvd2d8oSyU6sRLOK4f/9ZUeqPu19 oTVlTlkA15M3qc1TiKgWU4OC12Nx/Eai/AoNHyCVaa04nCB3bu167x5/kWOe3GaSPVSi GGNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689766559; x=1690371359; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ex8kAjQsuTgLkE/S9ECXNbIEk2g1m62Eq0yrmysJuO4=; b=Q694TrhqJnfXR5bem+3sBDXuilXiIW420OQTAWncjO2bHzlNd8Gwxz1/b3PmYsnBpT fQqFvUmWMe9r7WUF8AVgRc5Pa9tG8bbuTzeSpowCwpC9dOTyuXTCafNAtI5zUDivevbt iHIzQSjhQUrsQavf6sMWmeinFthpRyWBF2C5ErMPEZGQa2ohJTr5yxPljJoErXBSHEa/ D/cS1ryaGDZXSDnp6Gx7WDywf8lNHVL9+ZokTjfGz9UCs0czT5IoQ6iu4CNiTYqOH4EQ CsqRX5VP8qQeTscGD3CRZboxbsDkDeeLcNPw+Z59uqXsJdifieeY7Bt6u9EEcl0sN4D2 Vcvw== X-Gm-Message-State: ABy/qLb4yc8ue17TCj5URontdL6U96fHqkyL0616ahDY0k08b8eWrbll oazKdjdDNKyGEZc1Fw+PC1xSkaSVG0dWfDKLfRU= X-Google-Smtp-Source: APBJJlHE/gB3IcCwX8JyA+Se9kHRCxoLnrcDhdJVi4BAGxqm0X27B56ReTMccHezF5RTF20r1eTToA== X-Received: by 2002:a05:6a00:228e:b0:668:7292:b2c4 with SMTP id f14-20020a056a00228e00b006687292b2c4mr25389072pfe.4.1689766559249; Wed, 19 Jul 2023 04:35:59 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([171.76.86.130]) by smtp.gmail.com with ESMTPSA id j10-20020aa783ca000000b00669c99d05fasm3050408pfn.150.2023.07.19.04.35.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Jul 2023 04:35:58 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Frank Rowand , Conor Dooley Cc: Atish Patra , Andrew Jones , Sunil V L , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel Subject: [PATCH v6 01/14] RISC-V: Add riscv_get_intc_hartid() function Date: Wed, 19 Jul 2023 17:05:29 +0530 Message-Id: <20230719113542.2293295-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230719113542.2293295-1-apatel@ventanamicro.com> References: <20230719113542.2293295-1-apatel@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org We add a common riscv_get_intc_hartid() which help device drivers to get hartid of the HART associated with a INTC (i.e. local interrupt controller) fwnode. This new function is more generic compared to the existing riscv_of_parent_hartid() function hence we also replace use of riscv_of_parent_hartid() with riscv_get_intc_hartid(). Signed-off-by: Anup Patel --- arch/riscv/include/asm/processor.h | 4 +++- arch/riscv/kernel/cpu.c | 19 ++++++++++++++++++- drivers/irqchip/irq-riscv-intc.c | 2 +- drivers/irqchip/irq-sifive-plic.c | 3 ++- 4 files changed, 24 insertions(+), 4 deletions(-) diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h index c950a8d9edef..662da1e112dd 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -79,7 +79,9 @@ static inline void wait_for_interrupt(void) struct device_node; int riscv_of_processor_hartid(struct device_node *node, unsigned long *hartid); int riscv_early_of_processor_hartid(struct device_node *node, unsigned long *hartid); -int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid); + +struct fwnode_handle; +int riscv_get_intc_hartid(struct fwnode_handle *node, unsigned long *hartid); extern void riscv_fill_hwcap(void); extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src); diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index a2fc952318e9..5d26430fbcbd 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -81,7 +81,8 @@ int riscv_early_of_processor_hartid(struct device_node *node, unsigned long *har * To achieve this, we walk up the DT tree until we find an active * RISC-V core (HART) node and extract the cpuid from it. */ -int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid) +static int riscv_of_parent_hartid(struct device_node *node, + unsigned long *hartid) { int rc; @@ -96,6 +97,22 @@ int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid) return -1; } +/* Find hart ID of the INTC fwnode. */ +int riscv_get_intc_hartid(struct fwnode_handle *node, unsigned long *hartid) +{ + int rc; + u64 temp; + + if (!is_of_node(node)) { + rc = fwnode_property_read_u64_array(node, "hartid", &temp, 1); + if (!rc) + *hartid = temp; + } else + rc = riscv_of_parent_hartid(to_of_node(node), hartid); + + return rc; +} + DEFINE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); unsigned long riscv_cached_mvendorid(unsigned int cpu_id) diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c index 4adeee1bc391..65f4a2afb381 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -143,7 +143,7 @@ static int __init riscv_intc_init(struct device_node *node, int rc; unsigned long hartid; - rc = riscv_of_parent_hartid(node, &hartid); + rc = riscv_get_intc_hartid(of_fwnode_handle(node), &hartid); if (rc < 0) { pr_warn("unable to find hart id for %pOF\n", node); return 0; diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index e1484905b7bd..56b0544b1f27 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -477,7 +477,8 @@ static int __init __plic_init(struct device_node *node, continue; } - error = riscv_of_parent_hartid(parent.np, &hartid); + error = riscv_get_intc_hartid(of_fwnode_handle(parent.np), + &hartid); if (error < 0) { pr_warn("failed to parse hart ID for context %d.\n", i); continue;