From patchwork Wed Jul 19 11:35:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 704423 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BCC7EC0015E for ; Wed, 19 Jul 2023 11:37:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230289AbjGSLhb (ORCPT ); Wed, 19 Jul 2023 07:37:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54646 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230295AbjGSLha (ORCPT ); Wed, 19 Jul 2023 07:37:30 -0400 Received: from mail-pf1-x435.google.com (mail-pf1-x435.google.com [IPv6:2607:f8b0:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6E0401737 for ; Wed, 19 Jul 2023 04:37:01 -0700 (PDT) Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-666ecf9a0ceso4591453b3a.2 for ; Wed, 19 Jul 2023 04:37:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1689766603; x=1690371403; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hqMLD6GnTmKyZf6qDJ2/qOFn7vKzTS5oYxh4x8Esfkk=; b=NN12gld9xeVSD1XqFYqqOkUsDLTAOj0BChmw1+LO9CBPoy65dIN72zPlCUuYmm/oH1 BCY/jD67qb6hcwtMqmHVe6fn9DAMB+ymN/4IuUBou9LDlg/OYKJkJwYCc0tKoA4mFQai +1k4PyeVVFgfFzVRSdYqeI/piNwuh5LLs4ByrddtO/6NzBHaIujdZLhww+uw3ehQgjzj S3HjM3q8VRa2brVvquULOSNzkZOrcFWe0BkzAxhKdX6ilEjIZJtbkQ8hbCfWzwQV4gBt sL6A55Jzl07cOON7oq38+AG6fW7DOr1sYGCnivE0UJQxVv9O78KiNEV5U7KrzVN7efa3 TzqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689766603; x=1690371403; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hqMLD6GnTmKyZf6qDJ2/qOFn7vKzTS5oYxh4x8Esfkk=; b=FnmkZsZ1VGFvTCYuvzDXorwkdldWV1LJMSjH+mRXc9D4I7/qaSbnc99RyqjIDPd3CV bc919ZJQI/wAZ7q9GRyRhYpE9bGCVmlY0YCLOP1I9wgYL623EScNZgrUZp1FTNhH4Dwc sHBf35aZT8X17Bfq/F8zeviMtu4sWm2KKxDtVo2yoKwI3xADxcc6Huv+yjEjA8eyvhPN VtTvexLDNgwur2CGc7GutlB8GTOew4ER4COV7TiAf3tbcb/NJvLUn61OZaa/fv0YIg9G oblSYGU3XJhnRbkA6gic6ZzggCPrafomf9Pa0XDRevNyh5OrUtwF9l0GzSamhj/2mCN5 F7KA== X-Gm-Message-State: ABy/qLbP5kgEHzRJCDbFCWzQfk0AcQWbEs3FVUXH4QDYW5/2kfhs8vV2 7SMAr1uU8vuUzWS+lk2oZ08dbQ== X-Google-Smtp-Source: APBJJlGr0yvfq1VSpM38ymZp6zXV9JVb0RyDgP5UE0cHxI5kUDfBNYULtOdQX28yVGzgM6T/qgfDkg== X-Received: by 2002:a05:6a21:6d8f:b0:137:7198:af9b with SMTP id wl15-20020a056a216d8f00b001377198af9bmr332146pzb.56.1689766603141; Wed, 19 Jul 2023 04:36:43 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([171.76.86.130]) by smtp.gmail.com with ESMTPSA id j10-20020aa783ca000000b00669c99d05fasm3050408pfn.150.2023.07.19.04.36.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Jul 2023 04:36:42 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Frank Rowand , Conor Dooley Cc: Atish Patra , Andrew Jones , Sunil V L , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel Subject: [PATCH v6 09/14] irqchip/riscv-imsic: Add support for PCI MSI irqdomain Date: Wed, 19 Jul 2023 17:05:37 +0530 Message-Id: <20230719113542.2293295-10-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230719113542.2293295-1-apatel@ventanamicro.com> References: <20230719113542.2293295-1-apatel@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Linux PCI framework requires it's own dedicated MSI irqdomain so let us create PCI MSI irqdomain as child of the IMSIC base irqdomain. Signed-off-by: Anup Patel --- drivers/irqchip/Kconfig | 7 ++++ drivers/irqchip/irq-riscv-imsic-platform.c | 48 ++++++++++++++++++++++ drivers/irqchip/irq-riscv-imsic-state.h | 1 + 3 files changed, 56 insertions(+) diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 8ef18be5f37b..d700980372ef 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -550,6 +550,13 @@ config RISCV_IMSIC select IRQ_DOMAIN_HIERARCHY select GENERIC_MSI_IRQ +config RISCV_IMSIC_PCI + bool + depends on RISCV_IMSIC + depends on PCI + depends on PCI_MSI + default RISCV_IMSIC + config EXYNOS_IRQ_COMBINER bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST diff --git a/drivers/irqchip/irq-riscv-imsic-platform.c b/drivers/irqchip/irq-riscv-imsic-platform.c index db896b6e51ff..02175e4e5cb9 100644 --- a/drivers/irqchip/irq-riscv-imsic-platform.c +++ b/drivers/irqchip/irq-riscv-imsic-platform.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -184,6 +185,39 @@ static const struct irq_domain_ops imsic_base_domain_ops = { .free = imsic_irq_domain_free, }; +#ifdef CONFIG_RISCV_IMSIC_PCI + +static void imsic_pci_mask_irq(struct irq_data *d) +{ + pci_msi_mask_irq(d); + irq_chip_mask_parent(d); +} + +static void imsic_pci_unmask_irq(struct irq_data *d) +{ + pci_msi_unmask_irq(d); + irq_chip_unmask_parent(d); +} + +static struct irq_chip imsic_pci_irq_chip = { + .name = "IMSIC-PCI", + .irq_mask = imsic_pci_mask_irq, + .irq_unmask = imsic_pci_unmask_irq, + .irq_eoi = irq_chip_eoi_parent, +}; + +static struct msi_domain_ops imsic_pci_domain_ops = { +}; + +static struct msi_domain_info imsic_pci_domain_info = { + .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | + MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI), + .ops = &imsic_pci_domain_ops, + .chip = &imsic_pci_irq_chip, +}; + +#endif + static struct irq_chip imsic_plat_irq_chip = { .name = "IMSIC-PLAT", }; @@ -208,12 +242,26 @@ static int __init imsic_irq_domains_init(struct device *dev) } irq_domain_update_bus_token(imsic->base_domain, DOMAIN_BUS_NEXUS); +#ifdef CONFIG_RISCV_IMSIC_PCI + /* Create PCI MSI domain */ + imsic->pci_domain = pci_msi_create_irq_domain(dev->fwnode, + &imsic_pci_domain_info, + imsic->base_domain); + if (!imsic->pci_domain) { + dev_err(dev, "failed to create IMSIC PCI domain\n"); + irq_domain_remove(imsic->base_domain); + return -ENOMEM; + } +#endif + /* Create Platform MSI domain */ imsic->plat_domain = platform_msi_create_irq_domain(dev->fwnode, &imsic_plat_domain_info, imsic->base_domain); if (!imsic->plat_domain) { dev_err(dev, "failed to create IMSIC platform domain\n"); + if (imsic->pci_domain) + irq_domain_remove(imsic->pci_domain); irq_domain_remove(imsic->base_domain); return -ENOMEM; } diff --git a/drivers/irqchip/irq-riscv-imsic-state.h b/drivers/irqchip/irq-riscv-imsic-state.h index 3170018949a8..ff3c377b9b33 100644 --- a/drivers/irqchip/irq-riscv-imsic-state.h +++ b/drivers/irqchip/irq-riscv-imsic-state.h @@ -31,6 +31,7 @@ struct imsic_priv { /* IRQ domains (created by platform driver) */ struct irq_domain *base_domain; + struct irq_domain *pci_domain; struct irq_domain *plat_domain; };