From patchwork Tue Jul 4 09:19:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Qiu X-Patchwork-Id: 699063 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 62031C0015E for ; Tue, 4 Jul 2023 09:19:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231888AbjGDJT5 convert rfc822-to-8bit (ORCPT ); Tue, 4 Jul 2023 05:19:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44160 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231857AbjGDJTz (ORCPT ); Tue, 4 Jul 2023 05:19:55 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 663D1136; Tue, 4 Jul 2023 02:19:52 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 1E140828C; Tue, 4 Jul 2023 17:19:51 +0800 (CST) Received: from EXMBX068.cuchost.com (172.16.6.68) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 4 Jul 2023 17:19:51 +0800 Received: from williamqiu-virtual-machine.starfivetech.com (171.223.208.138) by EXMBX068.cuchost.com (172.16.6.68) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 4 Jul 2023 17:19:50 +0800 From: William Qiu To: , , , CC: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Emil Renner Berthing , Linus Walleij , William Qiu Subject: [PATCH v1 1/2] dt-binding: spi: constrain minItems of clocks and clock-names Date: Tue, 4 Jul 2023 17:19:43 +0800 Message-ID: <20230704091948.85247-2-william.qiu@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230704091948.85247-1-william.qiu@starfivetech.com> References: <20230704091948.85247-1-william.qiu@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX068.cuchost.com (172.16.6.68) X-YovoleRuleAgent: yovoleflag Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The SPI controller only need apb_pclk clock to work properly on JH7110 SoC, so there add minItems whose value is equal to 1. Other platforms do not have this constraint. Signed-off-by: William Qiu --- Documentation/devicetree/bindings/spi/spi-pl022.yaml | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/spi-pl022.yaml b/Documentation/devicetree/bindings/spi/spi-pl022.yaml index 91e540a92faf..42bb34c39971 100644 --- a/Documentation/devicetree/bindings/spi/spi-pl022.yaml +++ b/Documentation/devicetree/bindings/spi/spi-pl022.yaml @@ -11,6 +11,7 @@ maintainers: allOf: - $ref: spi-controller.yaml# + - $ref: /schemas/arm/primecell.yaml# # We need a select here so we don't match all nodes with 'arm,primecell' select: @@ -34,12 +35,16 @@ properties: maxItems: 1 clocks: + minItems: 1 maxItems: 2 clock-names: - items: - - const: sspclk - - const: apb_pclk + oneOf: + - items: + - const: apb_pclk + - items: + - const: sspclk + - const: apb_pclk pl022,autosuspend-delay: description: delay in ms following transfer completion before the