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Fri, 30 Jun 2023 09:22:44 -0500 Received: from xhdakumarma40u.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.23 via Frontend Transport; Fri, 30 Jun 2023 09:22:40 -0500 From: Amit Kumar Mahapatra To: , , , , , , , CC: , , , , , , Amit Kumar Mahapatra Subject: [PATCH v4 1/2] dt-bindings: mtd: jedec, spi-nor: Add DT property to avoid setting SRWD bit in status register Date: Fri, 30 Jun 2023 19:52:32 +0530 Message-ID: <20230630142233.63585-2-amit.kumar-mahapatra@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230630142233.63585-1-amit.kumar-mahapatra@amd.com> References: <20230630142233.63585-1-amit.kumar-mahapatra@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT089:EE_|BL1PR12MB5969:EE_ X-MS-Office365-Filtering-Correlation-Id: 1b957189-6f40-4c9b-c363-08db797579b3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jun 2023 14:22:46.2234 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1b957189-6f40-4c9b-c363-08db797579b3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT089.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5969 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org If the WP# signal of the flash device is either not connected or is wrongly tied to GND (that includes internal pull-downs), and the software sets the status register write disable (SRWD) bit in the status register then the status register permanently becomes read-only. To avoid this added a new boolean DT property "no-wp". If this property is set in the DT then the software avoids setting the SRWD during status register write operation. Signed-off-by: Amit Kumar Mahapatra Reviewed-by: Conor Dooley Reviewed-by: Rob Herring Reviewed-by: Michael Walle --- .../devicetree/bindings/mtd/jedec,spi-nor.yaml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml index 89959e5c47ba..97344969b02d 100644 --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml @@ -70,6 +70,21 @@ properties: be used on such systems, to denote the absence of a reliable reset mechanism. + no-wp: + type: boolean + description: + The status register write disable (SRWD) bit in status register, combined + with the WP# signal, provides hardware data protection for the device. When + the SRWD bit is set to 1, and the WP# signal is either driven LOW or hard + strapped to LOW, the status register nonvolatile bits become read-only and + the WRITE STATUS REGISTER operation will not execute. The only way to exit + this hardware-protected mode is to drive WP# HIGH. If the WP# signal of the + flash device is not connected or is wrongly tied to GND (that includes internal + pull-downs) then status register permanently becomes read-only as the SRWD bit + cannot be reset. This boolean flag can be used on such systems to avoid setting + the SRWD bit while writing the status register. WP# signal hard strapped to GND + can be a valid use case. + reset-gpios: description: A GPIO line connected to the RESET (active low) signal of the device.