From patchwork Thu Jun 29 08:28:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 697770 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3EA22EB64DD for ; Thu, 29 Jun 2023 08:31:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232458AbjF2IbG (ORCPT ); Thu, 29 Jun 2023 04:31:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48916 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232660AbjF2Ia1 (ORCPT ); Thu, 29 Jun 2023 04:30:27 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6D5D32733; Thu, 29 Jun 2023 01:30:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1688027423; x=1719563423; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=19N0qNDtQxBiEwr1QgI1H4EeYKq+lA8J3+dC/I8+GXA=; b=fKrFIZ4qSKfeycJIESkN9ZVwb14A/g2Qi6S6iRtZNP6iIBicApRUjV4q RgLOqlS7DpKOZzqKzOuy7i8DChnwtDm2KmWgNCxva3n2BOI+XR+YWS6Lc yXsA0UKct6aobbUql/h66ghpExNra508wfZV5ZPotbLWSFNnWGOqkxQYG aVdps/sq29UiM/rrm8kd4wplRUTrKSMmK8TtwHPEaxfc09XmMeuAZrYM4 MJEOwlvXs+YRG8HiJdn52+iTjgVL+VwGi/vkItXj0JrpE14L3jnVKHLHF 72Opdb5A29k7ef6Ji/xqGhCiuA2KRWr8ysIo53HoqrH1cmiZEFLY0MpCe g==; X-IronPort-AV: E=Sophos;i="6.01,168,1684825200"; d="scan'208";a="220461351" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 29 Jun 2023 01:30:22 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Thu, 29 Jun 2023 01:30:11 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Thu, 29 Jun 2023 01:30:09 -0700 From: Conor Dooley To: CC: , , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Albert Ou , Andrew Jones , Heiko Stuebner , "Evan Green" , Sunil V L , , , Subject: [PATCH v2 09/10] RISC-V: try new extension properties in of_early_processor_hartid() Date: Thu, 29 Jun 2023 09:28:55 +0100 Message-ID: <20230629-steersman-denim-9427eca04e44@wendy> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230629-rebuttal-vagueness-a699deb7c7b3@wendy> References: <20230629-rebuttal-vagueness-a699deb7c7b3@wendy> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1585; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=19N0qNDtQxBiEwr1QgI1H4EeYKq+lA8J3+dC/I8+GXA=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDClzHQ5fdzgSvfBCmtG03eGaVsov3W68mr3acflL3j9PJf9V HFRr7ChlYRDjYJAVU2RJvN3XIrX+j8sO5563MHNYmUCGMHBxCsBEmLMYGe4/vs2m+q2M53vonZ1z41 9LXy1heD698LP9JtG7C99d/pLB8FdcJptxm9PcM9pasUcc48L8M8TYm+a7LVBjX1Z3Nj/8GB8A X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org To fully deprecate the kernel's use of "riscv,isa", of_early_processor_hartid() needs to first try using the new properties, before falling back to "riscv,isa". Reviewed-by: Andrew Jones Signed-off-by: Conor Dooley --- arch/riscv/kernel/cpu.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index d0dfd88221df..9a4f4a23afcd 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -61,8 +61,29 @@ int riscv_early_of_processor_hartid(struct device_node *node, unsigned long *har return -ENODEV; } + if (of_property_read_string(node, "riscv,isa-base", &isa)) + goto old_interface; + + if (IS_ENABLED(CONFIG_32BIT) && strncasecmp(isa, "rv32i", 5)) + return -ENODEV; + + if (IS_ENABLED(CONFIG_64BIT) && strncasecmp(isa, "rv64i", 5)) + return -ENODEV; + + if (!of_property_present(node, "riscv,isa-extensions")) + return -ENODEV; + + if (of_property_match_string(node, "riscv,isa-extensions", "i") < 0 || + of_property_match_string(node, "riscv,isa-extensions", "m") < 0 || + of_property_match_string(node, "riscv,isa-extensions", "a") < 0) + return -ENODEV; + + return 0; + +old_interface: if (of_property_read_string(node, "riscv,isa", &isa)) { - pr_warn("CPU with hartid=%lu has no \"riscv,isa\" property\n", *hart); + pr_warn("CPU with hartid=%lu has no \"riscv,isa-base\" or \"riscv,isa\" property\n", + *hart); return -ENODEV; }