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[83.9.31.165]) by smtp.gmail.com with ESMTPSA id eq21-20020a056512489500b004f4c3feb9fbsm1099235lfb.61.2023.06.22.04.57.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Jun 2023 04:57:57 -0700 (PDT) From: Konrad Dybcio Date: Thu, 22 Jun 2023 13:57:47 +0200 Subject: [PATCH 7/9] clk: qcom: gcc-msm8998: Don't poke at some BIMC GPU clocks MIME-Version: 1.0 Message-Id: <20230622-topic-8998clk-v1-7-5b7a0d6e98b1@linaro.org> References: <20230622-topic-8998clk-v1-0-5b7a0d6e98b1@linaro.org> In-Reply-To: <20230622-topic-8998clk-v1-0-5b7a0d6e98b1@linaro.org> To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jeffrey Hugo , Taniya Das Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1687435067; l=2115; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=xt2xPT5OWFY9FXJ7H/2LPYsGPu00r53wEVIqMuapaII=; b=2hr6uDLk8/eJg7nshvP5I7TXQUvGJL8vGwFfDFLbEISgkyuS7aAIb5FCtKRIygJ5N7EZdjXrW KWdmpt+lRi2ANl52Dl0WnNjZEpFIn2kDxSk8B92YxqJ2G82pnjvV3rB X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Linux should apparently not be concerned with gcc_gpu_bimc_gfx_src_clk and gcc_gpu_bimc_gfx_src_clk on MSM8998, as they're preconfigured for us. Unregister them to prevent issues. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gcc-msm8998.c | 28 ---------------------------- 1 file changed, 28 deletions(-) diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c index ef410f52f09f..980b5a1b58ae 100644 --- a/drivers/clk/qcom/gcc-msm8998.c +++ b/drivers/clk/qcom/gcc-msm8998.c @@ -2136,19 +2136,6 @@ static struct clk_branch gcc_gpu_bimc_gfx_clk = { }, }; -static struct clk_branch gcc_gpu_bimc_gfx_src_clk = { - .halt_reg = 0x7100c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x7100c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_bimc_gfx_src_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_gpu_cfg_ahb_clk = { .halt_reg = 0x71004, .halt_check = BRANCH_HALT_SKIP, @@ -2168,19 +2155,6 @@ static struct clk_branch gcc_gpu_cfg_ahb_clk = { }, }; -static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { - .halt_reg = 0x71018, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x71018, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_snoc_dvm_gfx_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_hmss_ahb_clk = { .halt_reg = 0x48000, .halt_check = BRANCH_HALT_VOTED, @@ -3032,9 +3006,7 @@ static struct clk_regmap *gcc_msm8998_clocks[] = { [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr, [GCC_GPU_BIMC_GFX_CLK] = &gcc_gpu_bimc_gfx_clk.clkr, - [GCC_GPU_BIMC_GFX_SRC_CLK] = &gcc_gpu_bimc_gfx_src_clk.clkr, [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, - [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, [GCC_HMSS_AHB_CLK] = &gcc_hmss_ahb_clk.clkr, [GCC_HMSS_AT_CLK] = &gcc_hmss_at_clk.clkr, [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr,