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[88.10.54.61]) by smtp.gmail.com with ESMTPSA id a3-20020a056000050300b003068f5cca8csm25198228wrf.94.2023.06.16.22.24.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Jun 2023 22:24:46 -0700 (PDT) From: Sergio Paracuellos To: linux-clk@vger.kernel.org Cc: linux-mips@vger.kernel.org, tsbogend@alpha.franken.de, john@phrozen.org, linux-kernel@vger.kernel.org, p.zabel@pengutronix.de, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, devicetree@vger.kernel.org, arinc.unal@arinc9.com Subject: [PATCH v4 8/9] mips: ralink: get cpu rate from new driver code Date: Sat, 17 Jun 2023 07:24:34 +0200 Message-Id: <20230617052435.359177-9-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230617052435.359177-1-sergio.paracuellos@gmail.com> References: <20230617052435.359177-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org At very early stage on boot, there is a need to set 'mips_hpt_frequency'. This timer frequency is a half of the CPU frequency. To get clocks properly set we need to call to 'of_clk_init()' and properly get cpu clock frequency afterwards. Depending on the SoC, CPU clock index in the clock provider is different being two for MT7620 SoC and one for the rest. Hence, adapt code to be aligned with new clock driver. Signed-off-by: Sergio Paracuellos --- arch/mips/ralink/clk.c | 26 +++++++++++++++++++------- 1 file changed, 19 insertions(+), 7 deletions(-) diff --git a/arch/mips/ralink/clk.c b/arch/mips/ralink/clk.c index 5b02bb7e0829..3d29e956f785 100644 --- a/arch/mips/ralink/clk.c +++ b/arch/mips/ralink/clk.c @@ -11,29 +11,41 @@ #include #include #include +#include #include #include "common.h" -void ralink_clk_add(const char *dev, unsigned long rate) +static int clk_cpu_index(void) { - struct clk *clk = clk_register_fixed_rate(NULL, dev, NULL, 0, rate); + if (ralink_soc == RALINK_UNKNOWN) + return -1; - if (!clk) - panic("failed to add clock"); + if (ralink_soc == MT762X_SOC_MT7620A || + ralink_soc == MT762X_SOC_MT7620N) + return 2; - clkdev_create(clk, NULL, "%s", dev); + return 1; } void __init plat_time_init(void) { + struct of_phandle_args clkspec; struct clk *clk; + int cpu_clk_idx; ralink_of_remap(); - ralink_clk_init(); - clk = clk_get_sys("cpu", NULL); + cpu_clk_idx = clk_cpu_index(); + if (cpu_clk_idx == -1) + panic("unable to get CPU clock index"); + + of_clk_init(NULL); + clkspec.np = of_find_node_by_name(NULL, "sysc"); + clkspec.args_count = 1; + clkspec.args[0] = cpu_clk_idx; + clk = of_clk_get_from_provider(&clkspec); if (IS_ERR(clk)) panic("unable to get CPU clock, err=%ld", PTR_ERR(clk)); pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000);