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[v1,4/6] dt-bindings: riscv: cpus: permit operating-points-v2

Message ID 20230610-jacket-king-486b50a4e01d@spud
State New
Headers show
Series dt-bindings: riscv: cpus: switch to unevaluatedProperties: false | expand

Commit Message

Conor Dooley June 10, 2023, 5:24 p.m. UTC 
From: Conor Dooley <conor.dooley@microchip.com>

To allow setting "unevaluatedProperties: false" for cpus.yaml, permit
the operating points property for RISC-V cpu nodes.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
 1 file changed, 1 insertion(+)
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 9bf2b72a9460..00d1e273f1a9 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -108,6 +108,7 @@  properties:
   # RISC-V has multiple properties for cache op block sizes as the sizes
   # differ between individual CBO extensions
   cache-op-block-size: false
+  operating-points-v2: true
   # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
   timebase-frequency: false