From patchwork Tue May 30 16:24:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 687051 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B637C77B7A for ; Tue, 30 May 2023 16:27:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233070AbjE3Q1E (ORCPT ); Tue, 30 May 2023 12:27:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41826 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233194AbjE3Q0R (ORCPT ); Tue, 30 May 2023 12:26:17 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C8F29E52; Tue, 30 May 2023 09:25:45 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 903F862D4F; Tue, 30 May 2023 16:25:44 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7C428C433A1; Tue, 30 May 2023 16:25:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1685463944; bh=FDkW4zNGMZwi/c89+nTAB6D8hXQY5K3rr93bqPpZoXg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=tdhYASDMLQxhGky0erhaR+9pTubo9yaRsv4tlci/YqEsWpBigm5uG4nOX3jyJF33P HPb/tLSVWHQwnuTgMPbLDIHrdjIxMMBfUqUkWxZtw098+d3Rf47Grhp+XgfZdJiRbY l07YWHelVGlAvaaKdJhP5kQmPSdL3uv9rcdqYep6hP78uB3SKgav3BVjjG6fV0RvLL FAox7bKAt/iQHVK3Td9FfF3Kn76AYgKiIkU0MNIi4B11OEk6J/0IQ8/FHKkY3dXAgp Ke+KpMEPik+thcY0v9Cf1XiJbJku7jKMBtnqjpAEAMUTKRr79EYxQAiOH2wVrt+AtL wyUdhvWgFXz7A== From: Vinod Koul To: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vinod Koul Subject: [PATCH v3 12/15] arm64: dts: qcom: sc8180x: Add display and gpu nodes Date: Tue, 30 May 2023 21:54:51 +0530 Message-Id: <20230530162454.51708-13-vkoul@kernel.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230530162454.51708-1-vkoul@kernel.org> References: <20230530162454.51708-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds gpu, gmu, gpucc, dispcc and finally the mdss node with dsi0/1, dp0/1 and edp subnodes as found in this SoC Co-developed-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Signed-off-by: Vinod Koul --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 658 ++++++++++++++++++++++++++ 1 file changed, 658 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index c73fb25f5af0..e8613a00fcab 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -4,7 +4,9 @@ * Copyright (c) 2020-2023, Linaro Limited */ +#include #include +#include #include #include #include @@ -2190,6 +2192,123 @@ tcsr_mutex: hwlock@1f40000 { #hwlock-cells = <1>; }; + gpu: gpu@2c00000 { + compatible = "qcom,adreno-680.1", "qcom,adreno"; + #stream-id-cells = <16>; + + reg = <0 0x02c00000 0 0x40000>; + reg-names = "kgsl_3d0_reg_memory"; + + interrupts = ; + + iommus = <&adreno_smmu 0 0xc01>; + + operating-points-v2 = <&gpu_opp_table>; + + interconnects = <&gem_noc MASTER_GRAPHICS_3D 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "gfx-mem"; + + qcom,gmu = <&gmu>; + status = "disabled"; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-514000000 { + opp-hz = /bits/ 64 <514000000>; + opp-level = ; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-level = ; + }; + + opp-461000000 { + opp-hz = /bits/ 64 <461000000>; + opp-level = ; + }; + + opp-405000000 { + opp-hz = /bits/ 64 <405000000>; + opp-level = ; + }; + + opp-315000000 { + opp-hz = /bits/ 64 <315000000>; + opp-level = ; + }; + + opp-256000000 { + opp-hz = /bits/ 64 <256000000>; + opp-level = ; + }; + + opp-177000000 { + opp-hz = /bits/ 64 <177000000>; + opp-level = ; + }; + }; + }; + + gmu: gmu@2c6a000 { + compatible="qcom,adreno-gmu-680.1", "qcom,adreno-gmu"; + + reg = <0 0x02c6a000 0 0x30000>, + <0 0x0b290000 0 0x10000>, + <0 0x0b490000 0 0x10000>; + reg-names = "gmu", + "gmu_pdc", + "gmu_pdc_seq"; + + interrupts = , + ; + interrupt-names = "hfi", "gmu"; + + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>; + clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; + + power-domains = <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names = "cx", "gx"; + + iommus = <&adreno_smmu 5 0xc00>; + + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-level = ; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-level = ; + }; + }; + }; + + gpucc: clock-controller@2c90000 { + compatible = "qcom,sc8180x-gpucc"; + reg = <0 0x02c90000 0 0x9000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + clock-names = "bi_tcxo", + "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + adreno_smmu: iommu@2ca0000 { compatible = "qcom,sc8180x-smmu-500", "arm,mmu-500"; reg = <0 0x02ca0000 0 0x10000>; @@ -2539,6 +2658,545 @@ usb_sec_dwc3: usb@a800000 { }; }; + mdss: mdss@ae00000 { + compatible = "qcom,sc8180x-mdss"; + reg = <0 0x0ae00000 0 0x1000>; + reg-names = "mdss"; + + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", + "bus", + "nrt_bus", + "core"; + + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>, + <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + + iommus = <&apps_smmu 0x800 0x420>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + mdss_mdp: mdp@ae01000 { + compatible = "qcom,sc8180x-dpu"; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "iface", + "bus", + "core", + "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <460000000>, + <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SC8180X_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf0_out: endpoint { + remote-endpoint = <&dp0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@2 { + reg = <2>; + dpu_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + + port@4 { + reg = <4>; + dpu_intf4_out: endpoint { + remote-endpoint = <&dp1_in>; + }; + }; + + port@5 { + reg = <5>; + dpu_intf5_out: endpoint { + remote-endpoint = <&edp_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-345000000 { + opp-hz = /bits/ 64 <345000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-460000000 { + opp-hz = /bits/ 64 <460000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + dsi0: dsi@ae94000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae94000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SC8180X_MMCX>; + + phys = <&dsi0_phy>; + phy-names = "dsi"; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + + dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + dsi0_phy: dsi-phy@ae94400 { + compatible = "qcom,dsi-phy-7nm"; + reg = <0 0x0ae94400 0 0x200>, + <0 0x0ae94600 0 0x280>, + <0 0x0ae94900 0 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + + dsi1: dsi@ae96000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae96000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SC8180X_MMCX>; + + phys = <&dsi1_phy>; + phy-names = "dsi"; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + dsi1_out: endpoint { + }; + }; + }; + }; + + dsi1_phy: dsi-phy@ae96400 { + compatible = "qcom,dsi-phy-7nm"; + reg = <0 0x0ae96400 0 0x200>, + <0 0x0ae96600 0 0x280>, + <0 0x0ae96900 0 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + + mdss_dp0: displayport-controller@ae90000 { + compatible = "qcom,sc8180x-dp"; + reg = <0 0xae90000 0 0x200>, + <0 0xae90200 0 0x200>, + <0 0xae90400 0 0x600>, + <0 0xae90a00 0 0x400>; + interrupt-parent = <&mdss>; + interrupts = <12>; + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; + assigned-clock-parents = <&usb_prim_dpphy 0>, <&usb_prim_dpphy 1>; + + phys = <&usb_prim_dpphy>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + operating-points-v2 = <&dp0_opp_table>; + power-domains = <&rpmhpd SC8180X_CX>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dp0_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + + dp0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_dp1: displayport-controller@ae98000 { + compatible = "qcom,sc8180x-dp"; + reg = <0 0xae98000 0 0x200>, + <0 0xae98200 0 0x200>, + <0 0xae98400 0 0x600>, + <0 0xae98a00 0 0x400>; + interrupt-parent = <&mdss>; + interrupts = <13>; + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DP_AUX1_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK1_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>; + assigned-clock-parents = <&usb_sec_dpphy 0>, <&usb_sec_dpphy 1>; + + phys = <&usb_sec_dpphy>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + operating-points-v2 = <&dp0_opp_table>; + power-domains = <&rpmhpd SC8180X_CX>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dp1_in: endpoint { + remote-endpoint = <&dpu_intf4_out>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + + dp1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_edp: displayport-controller@ae9a000 { + compatible = "qcom,sc8180x-edp"; + reg = <0 0xae9a000 0 0x200>, + <0 0xae9a200 0 0x200>, + <0 0xae9a400 0 0x600>, + <0 0xae9aa00 0 0x400>; + interrupt-parent = <&mdss>; + interrupts = <14>; + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, + <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; + assigned-clock-parents = <&edp_phy 0>, <&edp_phy 1>; + + phys = <&edp_phy>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + operating-points-v2 = <&edp_opp_table>; + power-domains = <&rpmhpd SC8180X_CX>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + edp_in: endpoint { + remote-endpoint = <&dpu_intf5_out>; + }; + }; + }; + + edp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + }; + + edp_phy: phy@aec2a00 { + compatible = "qcom,sc8180x-edp-phy"; + reg = <0 0x0aec2a00 0 0x1c0>, + <0 0x0aec2200 0 0xa0>, + <0 0x0aec2600 0 0xa0>, + <0 0x0aec2000 0 0x19c>; + + clocks = <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>; + clock-names = "aux", "cfg_ahb"; + + power-domains = <&dispcc MDSS_GDSC>; + + #clock-cells = <1>; + #phy-cells = <0>; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,sc8180x-dispcc"; + reg = <0 0x0af00000 0 0x20000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <&usb_prim_dpphy 0>, + <&usb_prim_dpphy 1>, + <&usb_sec_dpphy 0>, + <&usb_sec_dpphy 1>, + <&edp_phy 0>, + <&edp_phy 1>; + clock-names = "bi_tcxo", + "sleep_clk", + "dp_phy_pll_link_clk", + "dp_phy_pll_vco_div_clk", + "dptx1_phy_pll_link_clk", + "dptx1_phy_pll_vco_div_clk", + "edp_phy_pll_link_clk", + "edp_phy_pll_vco_div_clk"; + power-domains = <&rpmhpd SC8180X_MMCX>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sc8180x-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>;