From patchwork Fri May 26 14:54:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Walker Chen X-Patchwork-Id: 686180 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3ADC5C7EE2C for ; Fri, 26 May 2023 14:54:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242934AbjEZOyS (ORCPT ); Fri, 26 May 2023 10:54:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45856 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237366AbjEZOyR (ORCPT ); Fri, 26 May 2023 10:54:17 -0400 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D5F7F1A2; Fri, 26 May 2023 07:54:13 -0700 (PDT) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id A8FD924E203; Fri, 26 May 2023 22:54:06 +0800 (CST) Received: from EXMBX168.cuchost.com (172.16.6.78) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 26 May 2023 22:54:06 +0800 Received: from SD-Server.starfivetech.com (183.27.98.143) by EXMBX168.cuchost.com (172.16.6.78) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 26 May 2023 22:54:05 +0800 From: Walker Chen To: Mark Brown , Liam Girdwood , Claudiu Beznea , Jaroslav Kysela , Takashi Iwai , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Emil Renner Berthing , Hal Feng , Walker Chen CC: , , , Subject: [PATCH v5 3/3] riscv: dts: starfive: add the node and pins configuration for tdm Date: Fri, 26 May 2023 22:54:02 +0800 Message-ID: <20230526145402.450-4-walker.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230526145402.450-1-walker.chen@starfivetech.com> References: <20230526145402.450-1-walker.chen@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.98.143] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX168.cuchost.com (172.16.6.78) X-YovoleRuleAgent: yovoleflag Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the tdm controller node and pins configuration of tdm for the StarFive JH7110 SoC. Signed-off-by: Walker Chen --- .../jh7110-starfive-visionfive-2.dtsi | 40 +++++++++++++++++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 21 ++++++++++ 2 files changed, 61 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index 1155b97b593d..19b5954ee72d 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -214,6 +214,40 @@ slew-rate = <0>; }; }; + + tdm0_pins: tdm0-pins { + tdm0-pins-tx { + pinmux = ; + bias-pull-up; + drive-strength = <2>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + + tdm0-pins-rx { + pinmux = ; + input-enable; + }; + + tdm0-pins-sync { + pinmux = ; + input-enable; + }; + + tdm0-pins-pcmclk { + pinmux = ; + input-enable; + }; + }; }; &uart0 { @@ -221,3 +255,9 @@ pinctrl-0 = <&uart0_pins>; status = "okay"; }; + +&tdm { + pinctrl-names = "default"; + pinctrl-0 = <&tdm0_pins>; + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 866313570a7e..cfda6fb0d91b 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -366,6 +366,27 @@ status = "disabled"; }; + tdm: tdm@10090000 { + compatible = "starfive,jh7110-tdm"; + reg = <0x0 0x10090000 0x0 0x1000>; + clocks = <&syscrg JH7110_SYSCLK_TDM_AHB>, + <&syscrg JH7110_SYSCLK_TDM_APB>, + <&syscrg JH7110_SYSCLK_TDM_INTERNAL>, + <&syscrg JH7110_SYSCLK_TDM_TDM>, + <&syscrg JH7110_SYSCLK_MCLK_INNER>, + <&tdm_ext>; + clock-names = "tdm_ahb", "tdm_apb", + "tdm_internal", "tdm", + "mclk_inner", "tdm_ext"; + resets = <&syscrg JH7110_SYSRST_TDM_AHB>, + <&syscrg JH7110_SYSRST_TDM_APB>, + <&syscrg JH7110_SYSRST_TDM_CORE>; + dmas = <&dma 20>, <&dma 21>; + dma-names = "rx","tx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + stgcrg: clock-controller@10230000 { compatible = "starfive,jh7110-stgcrg"; reg = <0x0 0x10230000 0x0 0x10000>;