From patchwork Thu May 18 15:22:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 683504 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D7827C7EE2A for ; Thu, 18 May 2023 15:35:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231947AbjERPfG (ORCPT ); Thu, 18 May 2023 11:35:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56518 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231915AbjERPeo (ORCPT ); Thu, 18 May 2023 11:34:44 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 92FA81708; Thu, 18 May 2023 08:34:25 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 1C40865026; Thu, 18 May 2023 15:34:25 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 765F6C433D2; Thu, 18 May 2023 15:34:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684424064; bh=9ZVQaWxp1rntSaFGKdgAUvSryPweqDi/a9hnkE1Whk8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=D4BGUnHoEQEDOGv3XS0kZ4uAw6KKAZfdXAGaQPtSUtMmLl3CSgyHra2G/dbS4zjEP 7IM/IREhAVbAdxAWoacPwlwRvTT1EDKdw6XiIPQIZWyeFM4l60NoHTqzAYpCmmF3Be nCizjtQqcqxf4ZsF38r6P5Nrobvb743GjexYMlsaWKqp99dktup1pgIxMi5kEimUwK fD7phZT913VUV2jDw9fP2QExGcyZk9NAdRUhr4+7sTiOxDlZ6rULA3bRoa0Foi+pXR 65byqHOuO8mVq2AGA8aCNe/HtxG8FRnNCs7QogZ74Neb7UKzV8J6SJSIJt4wMgFtwv WdjLR9z9joeCQ== From: Jisheng Zhang To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Greg Kroah-Hartman , Jiri Slaby Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-serial@vger.kernel.org, Palmer Dabbelt Subject: [PATCH v4 07/10] riscv: dts: bouffalolab: add the bl808 SoC base device tree Date: Thu, 18 May 2023 23:22:41 +0800 Message-Id: <20230518152244.2178-8-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230518152244.2178-1-jszhang@kernel.org> References: <20230518152244.2178-1-jszhang@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a baisc dtsi for the bouffalolab bl808 SoC. Signed-off-by: Jisheng Zhang Acked-by: Palmer Dabbelt --- arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 73 ++++++++++++++++++++++ 1 file changed, 73 insertions(+) create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808.dtsi diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi new file mode 100644 index 000000000000..87906fe51db5 --- /dev/null +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2022 Jisheng Zhang + */ + +#include + +/ { + compatible = "bouffalolab,bl808"; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + timebase-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "thead,c906", "riscv"; + device_type = "cpu"; + reg = <0>; + d-cache-block-size = <64>; + d-cache-sets = <256>; + d-cache-size = <32768>; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <32768>; + mmu-type = "riscv,sv39"; + riscv,isa = "rv64imafdc"; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + }; + + xtal: xtal-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + soc { + compatible = "simple-bus"; + ranges; + interrupt-parent = <&plic>; + dma-noncoherent; + #address-cells = <1>; + #size-cells = <1>; + + uart3: serial@30002000 { + compatible = "bouffalolab,bl808-uart"; + reg = <0x30002000 0x1000>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&xtal>; + status = "disabled"; + }; + + plic: interrupt-controller@e0000000 { + compatible = "bouffalolab,bl808-plic", "thead,c900-plic"; + reg = <0xe0000000 0x4000000>; + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + riscv,ndev = <82>; + }; + }; +};