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Wed, 17 May 2023 16:17:14 +0000 From: Frank Li To: vkoul@kernel.org Cc: Frank.Li@nxp.com, devicetree@vger.kernel.org, fushi.peng@nxp.com, imx@lists.linux.dev, kernel@pengutronix.de, kishon@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, robh+dt@kernel.org, s.hauer@pengutronix.de, shawnguo@kernel.org Subject: [PATCH v5 2/6] phy: cadence: salvo: decrease delay value to zero for txvalid Date: Wed, 17 May 2023 12:16:42 -0400 Message-Id: <20230517161646.3418250-3-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230517161646.3418250-1-Frank.Li@nxp.com> References: <20230517161646.3418250-1-Frank.Li@nxp.com> X-ClientProxiedBy: SJ0PR03CA0041.namprd03.prod.outlook.com (2603:10b6:a03:33e::16) To AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB4838:EE_|DB9PR04MB9962:EE_ X-MS-Office365-Filtering-Correlation-Id: bc523e6e-c651-4331-6a7d-08db56f22cfd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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The reason is the delay time between PHY powers up and txvalid is 20us. To fix it, we change the delay value as 0us. Signed-off-by: Peter Chen Signed-off-by: Frank Li --- drivers/phy/cadence/phy-cadence-salvo.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/phy/cadence/phy-cadence-salvo.c b/drivers/phy/cadence/phy-cadence-salvo.c index 06c5dbdb700e..2e3d4d8fb8eb 100644 --- a/drivers/phy/cadence/phy-cadence-salvo.c +++ b/drivers/phy/cadence/phy-cadence-salvo.c @@ -89,8 +89,20 @@ #define TB_ADDR_XCVR_DIAG_LANE_FCM_EN_MGN_TMR 0x40f2 #define TB_ADDR_TX_RCVDETSC_CTRL 0x4124 +/* USB2 PHY register definition */ +#define UTMI_REG15 0xaf + /* TB_ADDR_TX_RCVDETSC_CTRL */ #define RXDET_IN_P3_32KHZ BIT(0) +/* + * UTMI_REG15 + * + * Gate how many us for the txvalid signal until analog + * HS/FS transmitters have powered up + */ +#define TXVALID_GATE_THRESHOLD_HS_MASK (BIT(4) | BIT(5)) +/* 0us, txvalid is ready just after HS/FS transmitters have powered up */ +#define TXVALID_GATE_THRESHOLD_HS_0US (BIT(4) | BIT(5)) struct cdns_reg_pairs { u16 val; @@ -230,6 +242,11 @@ static int cdns_salvo_phy_init(struct phy *phy) cdns_salvo_write(salvo_phy, USB3_PHY_OFFSET, TB_ADDR_TX_RCVDETSC_CTRL, RXDET_IN_P3_32KHZ); + value = cdns_salvo_read(salvo_phy, USB2_PHY_OFFSET, UTMI_REG15); + value &= ~TXVALID_GATE_THRESHOLD_HS_MASK; + cdns_salvo_write(salvo_phy, USB2_PHY_OFFSET, UTMI_REG15, + value | TXVALID_GATE_THRESHOLD_HS_0US); + udelay(10); clk_disable_unprepare(salvo_phy->clk);