From patchwork Wed May 10 13:28:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Minda Chen X-Patchwork-Id: 680666 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EB677C7EE22 for ; Wed, 10 May 2023 13:28:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237092AbjEJN2d (ORCPT ); Wed, 10 May 2023 09:28:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35668 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237082AbjEJN2c (ORCPT ); Wed, 10 May 2023 09:28:32 -0400 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D0CB861B2; Wed, 10 May 2023 06:28:22 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id D411D24E143; Wed, 10 May 2023 21:28:18 +0800 (CST) Received: from EXMBX171.cuchost.com (172.16.6.91) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 10 May 2023 21:28:18 +0800 Received: from ubuntu.localdomain (183.27.98.219) by EXMBX171.cuchost.com (172.16.6.91) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 10 May 2023 21:28:17 +0800 From: Minda Chen To: Rob Herring , Krzysztof Kozlowski , Pawel Laszczak , Greg Kroah-Hartman , Peter Chen , Roger Quadros , Philipp Zabel CC: , , , Minda Chen Subject: [PATCH v2 1/2] dt-bindings: cdns,usb3: Add clock and reset Date: Wed, 10 May 2023 21:28:15 +0800 Message-ID: <20230510132816.108820-2-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230510132816.108820-1-minda.chen@starfivetech.com> References: <20230510132816.108820-1-minda.chen@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.98.219] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX171.cuchost.com (172.16.6.91) X-YovoleRuleAgent: yovoleflag Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org To support generic clock and reset init in Cadence USBSS controller, add clock and reset dts configuration. Signed-off-by: Minda Chen --- .../devicetree/bindings/usb/cdns,usb3.yaml | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/cdns,usb3.yaml b/Documentation/devicetree/bindings/usb/cdns,usb3.yaml index cae46c4982ad..623c6b34dee3 100644 --- a/Documentation/devicetree/bindings/usb/cdns,usb3.yaml +++ b/Documentation/devicetree/bindings/usb/cdns,usb3.yaml @@ -42,6 +42,18 @@ properties: - const: otg - const: wakeup + clocks: + minItems: 1 + maxItems: 8 + description: + USB controller clocks. + + resets: + minItems: 1 + maxItems: 8 + description: + USB controller generic resets. + dr_mode: enum: [host, otg, peripheral] @@ -98,5 +110,7 @@ examples: interrupt-names = "host", "peripheral", "otg"; maximum-speed = "super-speed"; dr_mode = "otg"; + clocks = <&clk 1>, <&clk 2>, <&clk 3>; + resets = <&rst 1>, <&rst 2>, <&rst 3>; }; };