From patchwork Tue May 16 12:55:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 683658 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88955C77B75 for ; Tue, 16 May 2023 12:56:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233279AbjEPM4Q (ORCPT ); Tue, 16 May 2023 08:56:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38202 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232206AbjEPM4M (ORCPT ); Tue, 16 May 2023 08:56:12 -0400 Received: from mail-lj1-x22d.google.com (mail-lj1-x22d.google.com [IPv6:2a00:1450:4864:20::22d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1A31B10D0 for ; Tue, 16 May 2023 05:55:46 -0700 (PDT) Received: by mail-lj1-x22d.google.com with SMTP id 38308e7fff4ca-2ac8ee9cf7aso131639011fa.2 for ; Tue, 16 May 2023 05:55:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684241741; x=1686833741; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=qVQkPRqRwG5xBfBm9IYhXXbdgn9DcrnRu4p8iX6QF0c=; b=IyMHltUlP9uKObnRhXsIyR5xuvuy5bjKsO1TBpsgEY0lojsUh6azozyNnSwoqRDWgZ Gn8vJavea3cp8JfBWPWuaTPwvTQy/F2fa3VEUu6XXxJpOhZj6RBsqNtJynV9+Mf4pDY0 OBsSQ6/2CyfHkwAlJFgBaGhlWOLk1dmsACou6FFkIX90DCvG6gjXXjg888ssICey6CZX Gw3UjaqfFgr/g/oJxHYAGhekljVkZUgwHhB5b122Lp7GbHvgRnmtUb5eptJzX4S+g8Dz KB42QhcGnkjbEYhaFvz8YXR20ggRESG8cnBpztR//BQCIaoAlLvdgHjlzGql61lrW+uR 3LAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684241741; x=1686833741; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qVQkPRqRwG5xBfBm9IYhXXbdgn9DcrnRu4p8iX6QF0c=; b=ejLYNmw5ut+XWrhLHuxFt7DBv2B1yOpvlxnZBi75pNGC3jPsKW15eg0+2tZl3SE1Yn n65i6N6kfHie59IRW7u16Od9Ij/UgSogeEeawYSIfPO5EiDq6+1vEX8YxWHVKgi2haMW xD1rnBYrnAKfzkiyc2sxj1pwdySORD2zjsvwp8sQQls7pkIqBgJkWG0US+vcwss0uGFB 7tusWgl9wtFj3b3nAm/LoMTwNOrQQi6+pEaGTgg/w3o61qt0ZPQF8YNPcVtVQp+jEi67 +WwUIGVvBpzAMIg81x4kw4JFvjXW10n07vJic7JyDhmWHYLe99eDYLR023hY9ZJEYWlA vWCQ== X-Gm-Message-State: AC+VfDy9TZwkuznbfrMxdVGayJWD2HUsLPx5ly8NGfp7TKjFW9Xs+yR/ Q6Yr30OtiWyXigSzmI55h2tu6g== X-Google-Smtp-Source: ACHHUZ7RhEWIXLYECAhT2ZQwH8jf4ikc6qKU6EfvQP9IF9TiXwnukvQW7I4p7F6775X3q8QBbqKciQ== X-Received: by 2002:a2e:80c6:0:b0:2a6:2444:9892 with SMTP id r6-20020a2e80c6000000b002a624449892mr8100808ljg.25.1684241741373; Tue, 16 May 2023 05:55:41 -0700 (PDT) Received: from [192.168.1.2] (c-05d8225c.014-348-6c756e10.bbcust.telenor.se. [92.34.216.5]) by smtp.gmail.com with ESMTPSA id o23-20020a2e7317000000b002add1f4a92asm1647789ljc.113.2023.05.16.05.55.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 05:55:40 -0700 (PDT) From: Linus Walleij Date: Tue, 16 May 2023 14:55:32 +0200 Subject: [PATCH v3 2/7] dmaengine: ste_dma40: Get LCPA SRAM from SRAM node MIME-Version: 1.0 Message-Id: <20230417-ux500-dma40-cleanup-v3-2-60bfa6785968@linaro.org> References: <20230417-ux500-dma40-cleanup-v3-0-60bfa6785968@linaro.org> In-Reply-To: <20230417-ux500-dma40-cleanup-v3-0-60bfa6785968@linaro.org> To: Vinod Koul , Rob Herring , Krzysztof Kozlowski Cc: dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Linus Walleij X-Mailer: b4 0.12.2 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Instead of passing the reserved SRAM as a "reg" field look for a phandle to the LCPA SRAM memory so we can use the proper SRAM device tree bindings for the SRAM. Signed-off-by: Linus Walleij --- drivers/dma/Kconfig | 1 + drivers/dma/ste_dma40.c | 47 ++++++++++++++++++++++++----------------------- 2 files changed, 25 insertions(+), 23 deletions(-) diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index f5f422f9b850..644c188d6a11 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -553,6 +553,7 @@ config STE_DMA40 bool "ST-Ericsson DMA40 support" depends on ARCH_U8500 select DMA_ENGINE + select SRAM help Support for ST-Ericsson DMA40 controller diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c index f093e08c23b1..7890ccae61f9 100644 --- a/drivers/dma/ste_dma40.c +++ b/drivers/dma/ste_dma40.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -3506,9 +3507,11 @@ static int __init d40_probe(struct platform_device *pdev) { struct stedma40_platform_data *plat_data = dev_get_platdata(&pdev->dev); struct device_node *np = pdev->dev.of_node; + struct device_node *np_lcpa; int ret = -ENOENT; struct d40_base *base; struct resource *res; + struct resource res_lcpa; int num_reserved_chans; u32 val; @@ -3535,37 +3538,37 @@ static int __init d40_probe(struct platform_device *pdev) spin_lock_init(&base->interrupt_lock); spin_lock_init(&base->execmd_lock); - /* Get IO for logical channel parameter address */ - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lcpa"); - if (!res) { - ret = -ENOENT; - d40_err(&pdev->dev, "No \"lcpa\" memory resource\n"); - goto destroy_cache; + /* Get IO for logical channel parameter address (LCPA) */ + np_lcpa = of_parse_phandle(np, "sram", 0); + if (!np_lcpa) { + dev_err(&pdev->dev, "no LCPA SRAM node\n"); + goto report_failure; } - base->lcpa_size = resource_size(res); - base->phy_lcpa = res->start; - - if (request_mem_region(res->start, resource_size(res), - D40_NAME " I/O lcpa") == NULL) { - ret = -EBUSY; - d40_err(&pdev->dev, "Failed to request LCPA region %pR\n", res); - goto destroy_cache; + /* This is no device so read the address directly from the node */ + ret = of_address_to_resource(np_lcpa, 0, &res_lcpa); + if (ret) { + dev_err(&pdev->dev, "no LCPA SRAM resource\n"); + goto report_failure; } + base->lcpa_size = resource_size(&res_lcpa); + base->phy_lcpa = res_lcpa.start; + dev_info(&pdev->dev, "found LCPA SRAM at 0x%08x, size 0x%08x\n", + (u32)base->phy_lcpa, base->lcpa_size); /* We make use of ESRAM memory for this. */ val = readl(base->virtbase + D40_DREG_LCPA); - if (res->start != val && val != 0) { + if (base->phy_lcpa != val && val != 0) { dev_warn(&pdev->dev, - "[%s] Mismatch LCPA dma 0x%x, def %pa\n", - __func__, val, &res->start); + "[%s] Mismatch LCPA dma 0x%x, def %08x\n", + __func__, val, (u32)base->phy_lcpa); } else - writel(res->start, base->virtbase + D40_DREG_LCPA); + writel(base->phy_lcpa, base->virtbase + D40_DREG_LCPA); - base->lcpa_base = ioremap(res->start, resource_size(res)); + base->lcpa_base = ioremap(base->phy_lcpa, base->lcpa_size); if (!base->lcpa_base) { ret = -ENOMEM; d40_err(&pdev->dev, "Failed to ioremap LCPA region\n"); - goto destroy_cache; + goto release_base; } /* If lcla has to be located in ESRAM we don't need to allocate */ if (base->plat_data->use_esram_lcla) { @@ -3678,9 +3681,7 @@ static int __init d40_probe(struct platform_device *pdev) if (base->lcpa_base) iounmap(base->lcpa_base); - if (base->phy_lcpa) - release_mem_region(base->phy_lcpa, - base->lcpa_size); +release_base: if (base->phy_start) release_mem_region(base->phy_start, base->phy_size);