From patchwork Sat Apr 15 11:13:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 674092 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7102C7619A for ; Sat, 15 Apr 2023 11:15:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230064AbjDOLPI (ORCPT ); Sat, 15 Apr 2023 07:15:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34142 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229623AbjDOLPG (ORCPT ); Sat, 15 Apr 2023 07:15:06 -0400 Received: from mout.gmx.net (mout.gmx.net [212.227.17.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 60C2A3C11; Sat, 15 Apr 2023 04:15:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=s31663417; t=1681557265; i=j.neuschaefer@gmx.net; bh=KTr1VzNMNDuistT9qUbHrDb1RsGIx4a1fQLKtGre52U=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=WlvMQCDHuxdg8r5nIJTldBMlFXy4l0H1LXSNL0pM0pCqDlK5c0Nok26OHxcuyjev5 ye3R46o80Xyqbc/rSjH33bIdHHQ67xVKxmwl7nhTOtUFrazgpRM0qTTxFYAgHs9B9z oT29KUKTgSK8Ag0Ur73oSawU6sXTIR9kMWsWYaZ06u04mocHFvJCc9pzBPfZBPHxCR SrjA4nmIRSOQavCQUa38GvomPnKxjG+d4VRDoWHYo3qhfug5a/4k1++pJ2+poMTcy6 Ejw3Ak9UovL9uuTlhAbBrXELhPamkE/NKbj5Okz8gbAgirViZ2pjMSjuVF9YDC0YBn Gs9+EgGltbs6w== X-UI-Sender-Class: 724b4f7f-cbec-4199-ad4e-598c01a50d3a Received: from probook ([95.223.44.193]) by mail.gmx.net (mrgmx105 [212.227.17.168]) with ESMTPSA (Nemesis) id 1M59GG-1pojn32btk-0016NW; Sat, 15 Apr 2023 13:14:25 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Daniel Lezcano , Thomas Gleixner , Philipp Zabel , Wim Van Sebroeck , Guenter Roeck , Krzysztof Kozlowski , Krzysztof Kozlowski Subject: [PATCH v6 1/2] dt-bindings: clock: Add Nuvoton WPCM450 clock/reset controller Date: Sat, 15 Apr 2023 13:13:54 +0200 Message-Id: <20230415111355.696738-2-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230415111355.696738-1-j.neuschaefer@gmx.net> References: <20230415111355.696738-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:3wh0mU/PJOHKFkGjd6InM4OxLev5AGa/cVCdQxa/Uv0KET7N9u6 8fkJG2ZETmEj4/QDM8Coy+LGTmY8i4WcUuXoZYFT+LHkIeyJmXT91KBYHnq8/Scdefr3lJy dEJksse/HS9hmV8/ZGs51VWqnzwz1Q9Zt8PWJ9dzQ90XMeic0r1+xH2YRiABRmnrheA70Dx fayiXHOXgeUsCRjCMYmiA== UI-OutboundReport: notjunk:1;M01:P0:ypaihKLgbIs=;TrAhl712aaNTAAlrNetD15z7M4R vBM2AjpdnBLddb/Bi8WBvr5rNX+bewHKTBH2ZRvueu3Reeexu3/HNs8mcncLXdvxKaXWQQSJa MwzFIfZGWoU3ep7NAazroUCUHlrNV1HltyxDEsuefi3HUmisRZPuoi7h4pYFXJ69budhC/2/7 AfXyak4HR9GmGjqa+hb2xiLrRaq8PJ5S7TIbUohv28N6vTSNL9c0UxzbfU8c6chBbT9ACDxzO S/ClLNLy7Yw3AgWpz/OWkzcP5XwARy3pE64BLSFM3UKcVSU1Wwy4MmpWE0TvOvd/iFNi88VDB lVaKPOJXX3ChwDKGS7zVV2hHtgq1DZ+EBvf5LO04DCO14IpTvO76MbdsMTWIAIidInK0rHo/Q ZnY1p1W/V2ZPj4ytMzJSFqZ93AnecKctisd2x9Kx+MgBmQl3XigIIjSOYg06hj816SLO+Zuw/ V9S+XgpGL3dNSPEw4SXUhr/5axy79dyhyG0ztL3pu78Ikf9iXMizrczvmvVZ8P9eBi5kL8rP4 gzBfpU9kTlDPt5QGeMWIJdlRUJIGEjCk7F+C0TRsPlUDBygisljCVPnEk6PNh7dhunsAGPakk Jw5+nXQYOO37xlyOoPNxAEbqBjdcP7vYlc6sP2H+Zc+OofhWnu5/sNN8gNxKH6Fctzus36EPU 9rUVMOMIM3E5QNuj7okbKrGX550IADOMEchm+xdtA7ZOBj97KWxAzarNCvYKE2ESm8BNWGk0T cHd3wdr7uYy0Xk6CClRJ4aBPQlgxiNjMNXej7x9Z0RfQwmOd+iYEgw/NvVNjvZAYThGRmf490 n5iie3KBFzHeWyj0NVnoMOJcY8FjQwJp9FJpXfJJ3m+n+kq41yO4qO8jh4iwtZqVnUVAaLXDe UAd4StPQSeEusOahiDeuaTnh8scQfaz1doVoU6aiWyqU2LtNy0KJM0Mjn0LgUOHtzTtEmDteS Xj/4bTpgwTiLOJDd+JzQVFBIOHM= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Nuvoton WPCM450 SoC has a combined clock and reset controller. Add a devicetree binding for it, as well as definitions for the bit numbers used by it. Signed-off-by: Jonathan Neuschäfer Reviewed-by: Krzysztof Kozlowski --- v5-v6: - no changes v4: - https://lore.kernel.org/lkml/20220610072141.347795-4-j.neuschaefer@gmx.net/ - Add R-b tag v3: - Change clock-output-names and clock-names from "refclk" to "ref", suggested by Krzysztof Kozlowski v2: - https://lore.kernel.org/lkml/20220429172030.398011-5-j.neuschaefer@gmx.net/ - Various improvements, suggested by Krzysztof Kozlowski v1: - https://lore.kernel.org/lkml/20220422183012.444674-5-j.neuschaefer@gmx.net/ --- .../bindings/clock/nuvoton,wpcm450-clk.yaml | 66 ++++++++++++++++++ .../dt-bindings/clock/nuvoton,wpcm450-clk.h | 67 +++++++++++++++++++ 2 files changed, 133 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml create mode 100644 include/dt-bindings/clock/nuvoton,wpcm450-clk.h -- 2.39.2 diff --git a/Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml b/Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml new file mode 100644 index 0000000000000..525024a58df4c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/nuvoton,wpcm450-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton WPCM450 clock controller + +maintainers: + - Jonathan Neuschäfer + +description: + The clock controller of the Nuvoton WPCM450 SoC supplies clocks and resets to + the rest of the chip. + +properties: + compatible: + const: nuvoton,wpcm450-clk + + reg: + maxItems: 1 + + clocks: + items: + - description: Reference clock oscillator (should be 48 MHz) + + clock-names: + items: + - const: ref + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +additionalProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +examples: + - | + #include + #include + + refclk: clock-48mhz { + /* 48 MHz reference oscillator */ + compatible = "fixed-clock"; + clock-output-names = "ref"; + clock-frequency = <48000000>; + #clock-cells = <0>; + }; + + clk: clock-controller@b0000200 { + reg = <0xb0000200 0x100>; + compatible = "nuvoton,wpcm450-clk"; + clocks = <&refclk>; + clock-names = "ref"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/clock/nuvoton,wpcm450-clk.h b/include/dt-bindings/clock/nuvoton,wpcm450-clk.h new file mode 100644 index 0000000000000..86e1c895921b7 --- /dev/null +++ b/include/dt-bindings/clock/nuvoton,wpcm450-clk.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLOCK_NUVOTON_WPCM450_CLK_H +#define _DT_BINDINGS_CLOCK_NUVOTON_WPCM450_CLK_H + +/* Clocks based on CLKEN bits */ +#define WPCM450_CLK_FIU 0 +#define WPCM450_CLK_XBUS 1 +#define WPCM450_CLK_KCS 2 +#define WPCM450_CLK_SHM 4 +#define WPCM450_CLK_USB1 5 +#define WPCM450_CLK_EMC0 6 +#define WPCM450_CLK_EMC1 7 +#define WPCM450_CLK_USB0 8 +#define WPCM450_CLK_PECI 9 +#define WPCM450_CLK_AES 10 +#define WPCM450_CLK_UART0 11 +#define WPCM450_CLK_UART1 12 +#define WPCM450_CLK_SMB2 13 +#define WPCM450_CLK_SMB3 14 +#define WPCM450_CLK_SMB4 15 +#define WPCM450_CLK_SMB5 16 +#define WPCM450_CLK_HUART 17 +#define WPCM450_CLK_PWM 18 +#define WPCM450_CLK_TIMER0 19 +#define WPCM450_CLK_TIMER1 20 +#define WPCM450_CLK_TIMER2 21 +#define WPCM450_CLK_TIMER3 22 +#define WPCM450_CLK_TIMER4 23 +#define WPCM450_CLK_MFT0 24 +#define WPCM450_CLK_MFT1 25 +#define WPCM450_CLK_WDT 26 +#define WPCM450_CLK_ADC 27 +#define WPCM450_CLK_SDIO 28 +#define WPCM450_CLK_SSPI 29 +#define WPCM450_CLK_SMB0 30 +#define WPCM450_CLK_SMB1 31 + +/* Other clocks */ +#define WPCM450_CLK_USBPHY 32 + +#define WPCM450_NUM_CLKS 33 + +/* Resets based on IPSRST bits */ +#define WPCM450_RESET_FIU 0 +#define WPCM450_RESET_EMC0 6 +#define WPCM450_RESET_EMC1 7 +#define WPCM450_RESET_USB0 8 +#define WPCM450_RESET_USB1 9 +#define WPCM450_RESET_AES_PECI 10 +#define WPCM450_RESET_UART 11 +#define WPCM450_RESET_MC 12 +#define WPCM450_RESET_SMB2 13 +#define WPCM450_RESET_SMB3 14 +#define WPCM450_RESET_SMB4 15 +#define WPCM450_RESET_SMB5 16 +#define WPCM450_RESET_PWM 18 +#define WPCM450_RESET_TIMER 19 +#define WPCM450_RESET_ADC 27 +#define WPCM450_RESET_SDIO 28 +#define WPCM450_RESET_SSPI 29 +#define WPCM450_RESET_SMB0 30 +#define WPCM450_RESET_SMB1 31 + +#define WPCM450_NUM_RESETS 32 + +#endif /* _DT_BINDINGS_CLOCK_NUVOTON_WPCM450_CLK_H */