From patchwork Fri Apr 14 06:16:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 674178 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9900BC77B7F for ; Fri, 14 Apr 2023 06:16:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230085AbjDNGQi (ORCPT ); Fri, 14 Apr 2023 02:16:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48830 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230099AbjDNGQg (ORCPT ); Fri, 14 Apr 2023 02:16:36 -0400 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 92B605FDE; Thu, 13 Apr 2023 23:16:34 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.99,195,1677510000"; d="scan'208";a="159411133" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 14 Apr 2023 15:16:32 +0900 Received: from localhost.localdomain (unknown [10.166.15.32]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 070EA4195D7C; Fri, 14 Apr 2023 15:16:32 +0900 (JST) From: Yoshihiro Shimoda To: jingoohan1@gmail.com, mani@kernel.org, gustavo.pimentel@synopsys.com, fancer.lancer@gmail.com, lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com, bhelgaas@google.com, kishon@kernel.org Cc: marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Yoshihiro Shimoda Subject: [PATCH v12 06/19] PCI: dwc: Add dw_pcie_link_set_max_cap_width() Date: Fri, 14 Apr 2023 15:16:09 +0900 Message-Id: <20230414061622.2930995-7-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230414061622.2930995-1-yoshihiro.shimoda.uh@renesas.com> References: <20230414061622.2930995-1-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add dw_pcie_link_set_max_cap_width() to set PCI_EXP_LNKCAP_MLW. In accordance with the DW PCIe RC/EP HW manuals [1,2,3,...] aside with the PORT_LINK_CTRL_OFF.LINK_CAPABLE and GEN2_CTRL_OFF.NUM_OF_LANES[8:0] field there is another one which needs to be update. It's LINK_CAPABILITIES_REG.PCIE_CAP_MAX_LINK_WIDTH. If it isn't done at the very least the maximum link-width capability CSR won't expose the actual maximum capability. [1] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port, Version 4.60a, March 2015, p.1032 [2] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port, Version 4.70a, March 2016, p.1065 [3] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port, Version 4.90a, March 2016, p.1057 ... [X] DesignWare Cores PCI Express Controller Databook - DWC PCIe Endpoint, Version 5.40a, March 2019, p.1396 [X+1] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port, Version 5.40a, March 2019, p.1266 The commit description is suggested by Serge Semin. Signed-off-by: Yoshihiro Shimoda --- drivers/pci/controller/dwc/pcie-designware.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 354e83352398..a33699a677e7 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -731,6 +731,21 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen) dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, cap | link_speed); } +void dw_pcie_link_set_max_cap_width(struct dw_pcie *pci, int num_lanes) +{ + u32 val; + u8 cap; + + if (!num_lanes) + return; + + cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + val = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP); + val &= ~PCI_EXP_LNKCAP_MLW; + val |= num_lanes << PCI_EXP_LNKSTA_NLW_SHIFT; + dw_pcie_writel_dbi(pci, cap + PCI_EXP_LNKCAP, val); +} + static void dw_pcie_link_set_max_width(struct dw_pcie *pci, u32 num_lanes) { u32 val; @@ -1067,6 +1082,7 @@ void dw_pcie_setup(struct dw_pcie *pci) dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val); } + dw_pcie_link_set_max_cap_width(pci, pci->num_lanes); dw_pcie_link_set_max_width(pci, pci->num_lanes); dw_pcie_link_set_max_link_width(pci, pci->num_lanes); }