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Ip=[20.160.56.81]; Helo=[inpost-eu.tmcas.trendmicro.com] X-MS-Exchange-CrossTenant-AuthSource: DB8EUR05FT054.eop-eur05.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR03MB7828 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds nodes for the SerDes devices. They are disabled by default to prevent any breakage on existing boards. Signed-off-by: Sean Anderson --- (no changes since v10) Changes in v10: - Move serdes bindings to SoC dtsi - Add support for all (ethernet) serdes modes - Refer to "nodes" instead of "bindings" - Move compatible/reg first Changes in v4: - Convert to new bindings Changes in v3: - New .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 126 ++++++++++++++++++ 1 file changed, 126 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index e5fb137ac02b..59b401daad4d 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -9,6 +9,7 @@ */ #include #include +#include #include / { @@ -238,6 +239,131 @@ reset: syscon@1e60000 { reg = <0x0 0x1e60000 0x0 0x10000>; }; + serdes1: serdes@1ea0000 { + compatible = "fsl,ls1088a-serdes", "fsl,lynx-10g"; + reg = <0x0 0x1ea0000 0x0 0x2000>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + status = "disabled"; + + /* + * XXX: Lane A uses pins SD1_RX3_P/N! That is, the lane + * numbers and pin numbers are _reversed_. + */ + serdes1_A: phy@0 { + #phy-cells = <0>; + reg = <0>; + + /* SG3 */ + sgmii-0 { + fsl,pccr = <0x8>; + fsl,index = <0>; + fsl,cfg = <0x1>; + fsl,type = ; + }; + + /* QSGb */ + qsgmii-0 { + fsl,pccr = <0x9>; + fsl,index = <0>; + fsl,cfg = <0x1>; + fsl,type = ; + }; + }; + + serdes1_B: phy@1 { + #phy-cells = <0>; + reg = <1>; + + /* SG7 */ + sgmii-1 { + fsl,pccr = <0x8>; + fsl,index = <1>; + fsl,cfg = <0x1>; + fsl,type = ; + }; + + /* QSGa */ + qsgmii-1 { + fsl,pccr = <0x9>; + fsl,index = <1>; + fsl,cfg = <0x1>; + fsl,type = ; + }; + + /* TODO: PCIe1 */ + }; + + serdes1_C: phy@2 { + #phy-cells = <0>; + reg = <2>; + + /* SG1 */ + sgmii-2 { + fsl,pccr = <0x8>; + fsl,index = <2>; + fsl,cfg = <0x1>; + fsl,type = ; + }; + + /* + * XFI1 + * Table 23-1 and section 23.5.16.4 disagree; + * this reflects the table. + * + * fsl,cfg is documented as 1, but it is set to + * 2 by the RCW! This is the same as the + * LS1046A. + */ + xfi-0 { + fsl,pccr = <0xb>; + fsl,index = <0>; + fsl,cfg = <0x2>; + fsl,type = ; + }; + }; + + serdes1_D: phy@3 { + #phy-cells = <0>; + reg = <3>; + + /* SG2 */ + sgmii-3 { + fsl,pccr = <0x8>; + fsl,index = <3>; + fsl,cfg = <0x1>; + fsl,type = ; + }; + + /* QSGb */ + qsgmii-0 { + fsl,pccr = <0x9>; + fsl,index = <0>; + fsl,cfg = <0x2>; + fsl,type = ; + }; + + /* XFI2 */ + xfi-1 { + fsl,pccr = <0xb>; + fsl,index = <1>; + fsl,cfg = <0x1>; + fsl,type = ; + }; + }; + + }; + + serdes2: serdes@1eb0000 { + compatible = "fsl,ls1088a-serdes", "fsl,lynx-10g"; + reg = <0x0 0x1eb0000 0x0 0x2000>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + status = "disabled"; + }; + isc: syscon@1f70000 { compatible = "fsl,ls1088a-isc", "syscon"; reg = <0x0 0x1f70000 0x0 0x10000>;