From patchwork Wed Apr 5 16:52:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 670568 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92C8BC76188 for ; Wed, 5 Apr 2023 16:52:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232822AbjDEQwq (ORCPT ); Wed, 5 Apr 2023 12:52:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58358 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229553AbjDEQwp (ORCPT ); Wed, 5 Apr 2023 12:52:45 -0400 Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6BD114C05 for ; Wed, 5 Apr 2023 09:52:43 -0700 (PDT) Received: from tr.lan (ip-86-49-120-218.bb.vodafone.cz [86.49.120.218]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 218D08579A; Wed, 5 Apr 2023 18:52:41 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1680713561; bh=qnVsJNQpgMfCjmE9rLKiLblLxwvxGkwtWG10VD0Lzsg=; h=From:To:Cc:Subject:Date:From; b=AOwZxA2r0EnrpwA21DroFYXa2g0KNsBlJRchKPr+ncEkByWCoZ9Veh8sT09l6mQkM Cw/wyWeWbydoV2IYWYETYZt1M/yBHfpuJwGa4ykltM/rhyZJbvYtwe6pzsd0e+Nqkm 4iXESZhfzi2VfEx4ZQowTi1SOjplaVQq/HJ2tIC6blCbUgTZCQnNfnxUvVNpDVet6X meXTjp9qi3J7cpXZYaLpfJoua1CcD0FbMOMFcZPrMCzkow447qbFxW9wqJcAt8aouJ D+XqtX7nwJDP+Y/dE1+7UEPSdHpgBl7OF2Eu/fBUcXqRUli4M3KwmRtqLS0d8pYOAM CgIcEpPLc4eIw== From: Marek Vasut To: linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , Alexander Stein , Fabio Estevam , Abel Vesa , Dong Aisheng , =?utf-8?q?Guido_G=C3=BCnther?= , Jagan Teki , Krzysztof Kozlowski , Lucas Stach , NXP Linux Team , Pengutronix Kernel Team , Richard Cochran , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org Subject: [PATCH v2 1/3] arm64: dts: imx8mm: Add display pipeline components Date: Wed, 5 Apr 2023 18:52:12 +0200 Message-Id: <20230405165214.95574-1-marex@denx.de> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add LCDIF scanout engine and DSIM bridge nodes for i.MX8M Mini. This makes the DSI display pipeline available on this SoC. Reviewed-by: Alexander Stein Reviewed-by: Fabio Estevam Signed-off-by: Marek Vasut --- Cc: Abel Vesa Cc: Alexander Stein Cc: Dong Aisheng Cc: Fabio Estevam Cc: Guido Günther Cc: Jagan Teki Cc: Krzysztof Kozlowski Cc: Lucas Stach Cc: NXP Linux Team Cc: Pengutronix Kernel Team Cc: Richard Cochran Cc: Rob Herring Cc: Sascha Hauer Cc: Shawn Guo Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org --- V2: - Drop the address-cells/size-cells from DSIM node - Add RB from Fabio, Alexander - CC Alexander, Jagan - Bundle the MX8MM,N,P patches together in one series --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 55 +++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index e311da7e87bdc..d6b36f04f3dc1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1119,6 +1119,61 @@ aips4: bus@32c00000 { #size-cells = <1>; ranges = <0x32c00000 0x32c00000 0x400000>; + lcdif: lcdif@32e00000 { + compatible = "fsl,imx8mm-lcdif", "fsl,imx6sx-lcdif"; + reg = <0x32e00000 0x10000>; + clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>, + <&clk IMX8MM_CLK_DISP_APB_ROOT>, + <&clk IMX8MM_CLK_DISP_AXI_ROOT>; + clock-names = "pix", "axi", "disp_axi"; + assigned-clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>, + <&clk IMX8MM_CLK_DISP_AXI>, + <&clk IMX8MM_CLK_DISP_APB>; + assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>, + <&clk IMX8MM_SYS_PLL2_1000M>, + <&clk IMX8MM_SYS_PLL1_800M>; + assigned-clock-rates = <594000000>, <500000000>, <200000000>; + interrupts = ; + power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_LCDIF>; + status = "disabled"; + + port { + lcdif_to_dsim: endpoint { + remote-endpoint = <&dsim_from_lcdif>; + }; + }; + }; + + mipi_dsi: dsi@32e10000 { + compatible = "fsl,imx8mm-mipi-dsim"; + reg = <0x32e10000 0x400>; + clocks = <&clk IMX8MM_CLK_DSI_CORE>, + <&clk IMX8MM_CLK_DSI_PHY_REF>; + clock-names = "bus_clk", "sclk_mipi"; + assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>, + <&clk IMX8MM_CLK_DSI_PHY_REF>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, + <&clk IMX8MM_CLK_24M>; + assigned-clock-rates = <266000000>, <24000000>; + samsung,pll-clock-frequency = <24000000>; + interrupts = ; + power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_DSI>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsim_from_lcdif: endpoint { + remote-endpoint = <&lcdif_to_dsim>; + }; + }; + }; + }; + csi: csi@32e20000 { compatible = "fsl,imx8mm-csi", "fsl,imx7-csi"; reg = <0x32e20000 0x1000>;