From patchwork Tue Apr 4 15:53:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Rokosov X-Patchwork-Id: 670192 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81D2EC77B72 for ; Tue, 4 Apr 2023 15:54:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235182AbjDDPyy (ORCPT ); Tue, 4 Apr 2023 11:54:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54724 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235832AbjDDPyt (ORCPT ); Tue, 4 Apr 2023 11:54:49 -0400 Received: from mx.sberdevices.ru (mx.sberdevices.ru [45.89.227.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DD9245255; Tue, 4 Apr 2023 08:54:20 -0700 (PDT) Received: from s-lin-edge02.sberdevices.ru (localhost [127.0.0.1]) by mx.sberdevices.ru (Postfix) with ESMTP id 2FC3B5FD11; Tue, 4 Apr 2023 18:53:45 +0300 (MSK) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sberdevices.ru; s=mail; t=1680623625; bh=QACcL2z5H0WiVPZBqWtG1qVoEZA/+FwC6rxiZKbXGhQ=; h=From:To:Subject:Date:Message-ID:MIME-Version:Content-Type; b=Ki2cStm4oUQf3Reu6+eRD7kp7pXii0FWmMRDrMfDt+fIQShazVV1wgmJG/uoIZuCV Vp+1bbUk3IBsVtbM/CSvx6nXw72cFlRKpXKOYtv14m3CHOemp8LI9dBv1lzgJn7VBm NPwhYAjcqRTy1kzyb+lGBM2XuaxReh5revetkLolsFqzgbiY4TsLnhB7fXhdChRrUq eDMlhYaxmVxrPavdthi2Oz4Ya3ITvXbNemfXmMdljobW5ZuovSBLIUQ0Qbagg4MT8X Kbk22SWBJ2BXCjuyMCDmncwtkubFtq3iZZcaAxSUBPq8yBq9Me1wiKtbt9yBRPGK4c KuNaTYW6PaetQ== Received: from S-MS-EXCH01.sberdevices.ru (S-MS-EXCH01.sberdevices.ru [172.16.1.4]) by mx.sberdevices.ru (Postfix) with ESMTP; Tue, 4 Apr 2023 18:53:45 +0300 (MSK) From: Dmitry Rokosov To: , , , , , , , CC: , , , , , , , , Dmitry Rokosov Subject: [PATCH v12 2/6] clk: meson: introduce new pll power-on sequence for A1 SoC family Date: Tue, 4 Apr 2023 18:53:28 +0300 Message-ID: <20230404155332.9571-3-ddrokosov@sberdevices.ru> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20230404155332.9571-1-ddrokosov@sberdevices.ru> References: <20230404155332.9571-1-ddrokosov@sberdevices.ru> MIME-Version: 1.0 X-Originating-IP: [172.16.1.6] X-ClientProxiedBy: S-MS-EXCH01.sberdevices.ru (172.16.1.4) To S-MS-EXCH01.sberdevices.ru (172.16.1.4) X-KSMG-Rule-ID: 4 X-KSMG-Message-Action: clean X-KSMG-AntiSpam-Status: not scanned, disabled by settings X-KSMG-AntiSpam-Interceptor-Info: not scanned X-KSMG-AntiPhishing: not scanned, disabled by settings X-KSMG-AntiVirus: Kaspersky Secure Mail Gateway, version 1.1.2.30, bases: 2023/04/04 13:20:00 #21030339 X-KSMG-AntiVirus-Status: Clean, skipped Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Modern meson PLL IPs are a little bit different from early known PLLs. The main difference is located in the init/enable/disable sequences; the rate logic is the same. In A1 PLL, the PLL enable sequence is different, so add new optional pll reg bits and use the new power-on sequence to enable the PLL: 1. enable the pll, delay for 10us 2. enable the pll self-adaption current module, delay for 40us 3. enable the lock detect module Signed-off-by: Jian Hu Acked-by: Martin Blumenstingl Signed-off-by: Dmitry Rokosov --- drivers/clk/meson/clk-pll.c | 23 +++++++++++++++++++++++ drivers/clk/meson/clk-pll.h | 2 ++ 2 files changed, 25 insertions(+) diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c index 314ca945a4d0..56ec2210f1ad 100644 --- a/drivers/clk/meson/clk-pll.c +++ b/drivers/clk/meson/clk-pll.c @@ -358,6 +358,25 @@ static int meson_clk_pll_enable(struct clk_hw *hw) if (MESON_PARM_APPLICABLE(&pll->rst)) meson_parm_write(clk->map, &pll->rst, 0); + /* + * Compared with the previous SoCs, self-adaption current module + * is newly added for A1, keep the new power-on sequence to enable the + * PLL. The sequence is: + * 1. enable the pll, delay for 10us + * 2. enable the pll self-adaption current module, delay for 40us + * 3. enable the lock detect module + */ + if (MESON_PARM_APPLICABLE(&pll->current_en)) { + usleep_range(10, 20); + meson_parm_write(clk->map, &pll->current_en, 1); + usleep_range(40, 50); + }; + + if (MESON_PARM_APPLICABLE(&pll->l_detect)) { + meson_parm_write(clk->map, &pll->l_detect, 1); + meson_parm_write(clk->map, &pll->l_detect, 0); + } + if (meson_clk_pll_wait_lock(hw)) return -EIO; @@ -375,6 +394,10 @@ static void meson_clk_pll_disable(struct clk_hw *hw) /* Disable the pll */ meson_parm_write(clk->map, &pll->en, 0); + + /* Disable PLL internal self-adaption current module */ + if (MESON_PARM_APPLICABLE(&pll->current_en)) + meson_parm_write(clk->map, &pll->current_en, 0); } static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, diff --git a/drivers/clk/meson/clk-pll.h b/drivers/clk/meson/clk-pll.h index 367efd0f6410..a2228c0fdce5 100644 --- a/drivers/clk/meson/clk-pll.h +++ b/drivers/clk/meson/clk-pll.h @@ -36,6 +36,8 @@ struct meson_clk_pll_data { struct parm frac; struct parm l; struct parm rst; + struct parm current_en; + struct parm l_detect; const struct reg_sequence *init_regs; unsigned int init_count; const struct pll_params_table *table;