From patchwork Thu Mar 30 20:42:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 668701 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BAA22C6FD1D for ; Thu, 30 Mar 2023 20:43:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229900AbjC3Um7 (ORCPT ); Thu, 30 Mar 2023 16:42:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44038 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229865AbjC3Umr (ORCPT ); Thu, 30 Mar 2023 16:42:47 -0400 Received: from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com [IPv6:2a00:1450:4864:20::32f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C203DE1AD; Thu, 30 Mar 2023 13:42:44 -0700 (PDT) Received: by mail-wm1-x32f.google.com with SMTP id s13so11672309wmr.4; Thu, 30 Mar 2023 13:42:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1680208963; x=1682800963; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XY5+OVya6TA6lYZwP/Dw+HpNzXeJslFUYk/NwxMBWvI=; b=HvctlR8Cda7IVjOw+XoME5aVHWmD+3Ipf3VGtEkDh8FEhl7tme/rciTW0vh/qYjNjz QecIgWzZPaZRKrGxZI/NDZ67y+CGIxeZj+IXXgA+q7duWCPmFTDtuJi8RKXdpnn6rzQc a8VuJYZ5JnB9xBD4raa9HRjGQyv/qchVcSSmWjHGbaZ6S8MFrICwGFcfSYTj4rbJBeku wl58ymvgpLdRnW5qLE16f/UcT552cJqDEWK3bsmeDfYGVF4Ma4QRy47PSG2uYEU3tj7/ Vgy8TZFkNz/Je72cquDySnuVARaGfF7TWoBCr0f0OYI90ealgyP3kMznMuyBeGBYFl/D 3zcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680208963; x=1682800963; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XY5+OVya6TA6lYZwP/Dw+HpNzXeJslFUYk/NwxMBWvI=; b=49XxuzySniIlu8jbXOF4pDLSnTCbmtYrjreccP59y+xY9ht1GRU+mgM+rsUpMW087H SBIELxFOFBS5dCOqpHs3+6kebLSi/esKaxPtVo9LGGi947aa6aC6pIdV2d4+4Iw/MS9r k1uVJTBdBAcLpwKeIvzaaTp2j8q8AsRvSF2SuCY0MwSvHmOAs8By+9GaByiASPTnBBpP kOuBz71KV0w5JQeNLF1KGtErLhvgt0sAC9dNnS43kfqSl7PKaoCis7KX20fAeqhpeNcP nR6jbHVN6/m5Qv8g2IjelKkLmcu2BO9E2v8KTZUtuQkJi5WneWIJt+YKb8zIMOSBrw9T 82hQ== X-Gm-Message-State: AAQBX9c4mbJgArcsJYkrNXffBSmx5g2YMlZqZhTqrD1y7lLx4UgJ1UcK GCV39WWFQrYv9pVwlh3Urtk= X-Google-Smtp-Source: AKy350ZfKliNEZJDftlXlfyGqMlmJouSxsPW8ShMtQhELBCFkAvoBP4EEgAlsXeT38L9RXyzp/oPVg== X-Received: by 2002:a1c:7310:0:b0:3ef:6df2:d174 with SMTP id d16-20020a1c7310000000b003ef6df2d174mr12323421wmb.12.1680208963175; Thu, 30 Mar 2023 13:42:43 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2501:c701:30f2:5b7:ab32:c3f]) by smtp.gmail.com with ESMTPSA id v12-20020a5d4b0c000000b002cfed482e9asm297981wrq.61.2023.03.30.13.42.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Mar 2023 13:42:42 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Arnd Bergmann , Conor Dooley , Geert Uytterhoeven , Heiko Stuebner , Guo Ren , Andrew Jones , Paul Walmsley , Palmer Dabbelt , Albert Ou , Samuel Holland , linux-riscv@lists.infradead.org Cc: Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v7 3/6] riscv: errata: Add Andes alternative ports Date: Thu, 30 Mar 2023 21:42:14 +0100 Message-Id: <20230330204217.47666-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230330204217.47666-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20230330204217.47666-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Lad Prabhakar Add required ports of the Alternative scheme for Andes CPU cores. I/O Coherence Port (IOCP) provides an AXI interface for connecting external non-caching masters, such as DMA controllers. IOCP is a specification option and is disabled on the Renesas RZ/Five SoC due to this reason cache management needs a software workaround. Signed-off-by: Lad Prabhakar Reviewed-by: Conor Dooley --- v6 -> v7 * Renamed RZFIVE_SBI_EXT_IOCP_SW_WORKAROUND -> ANDES_SBI_EXT_IOCP_SW_WORKAROUND * Dropped "depends on !XIP_KERNEL" for ERRATA_ANDES config v5 -> v6 * Dropped patching alternative and now just probing IOCP v4 -> v5 * Sorted the Kconfig/Makefile/Switch based on Core name * Added a comments * Introduced RZFIVE_SBI_EXT_IOCP_SW_WORKAROUND SBI EXT ID to check if CMO needs to be applied. Is there a way we can access the DTB while patching as we can drop this SBI EXT ID and add a DT property instead for cmo? RFC v3 -> v4 * New patch --- arch/riscv/Kconfig.errata | 21 ++++++++ arch/riscv/errata/Makefile | 1 + arch/riscv/errata/andes/Makefile | 1 + arch/riscv/errata/andes/errata.c | 71 ++++++++++++++++++++++++++++ arch/riscv/include/asm/alternative.h | 3 ++ arch/riscv/kernel/alternative.c | 5 ++ 6 files changed, 102 insertions(+) create mode 100644 arch/riscv/errata/andes/Makefile create mode 100644 arch/riscv/errata/andes/errata.c diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata index 0c8f4652cd82..92c779764b27 100644 --- a/arch/riscv/Kconfig.errata +++ b/arch/riscv/Kconfig.errata @@ -1,5 +1,26 @@ menu "CPU errata selection" +config ERRATA_ANDES + bool "Andes AX45MP errata" + depends on RISCV_ALTERNATIVE + help + All Andes errata Kconfig depend on this Kconfig. Disabling + this Kconfig will disable all Andes errata. Please say "Y" + here if your platform uses Andes CPU cores. + + Otherwise, please say "N" here to avoid unnecessary overhead. + +config ERRATA_ANDES_CMO + bool "Apply Andes cache management errata" + depends on ERRATA_ANDES && MMU && ARCH_R9A07G043 + select RISCV_DMA_NONCOHERENT + default y + help + This will apply the cache management errata to handle the + non-standard handling on non-coherent operations on Andes cores. + + If you don't know what to do here, say "Y". + config ERRATA_SIFIVE bool "SiFive errata" depends on RISCV_ALTERNATIVE diff --git a/arch/riscv/errata/Makefile b/arch/riscv/errata/Makefile index a1055965fbee..6f1c693af92d 100644 --- a/arch/riscv/errata/Makefile +++ b/arch/riscv/errata/Makefile @@ -1,2 +1,3 @@ +obj-$(CONFIG_ERRATA_ANDES) += andes/ obj-$(CONFIG_ERRATA_SIFIVE) += sifive/ obj-$(CONFIG_ERRATA_THEAD) += thead/ diff --git a/arch/riscv/errata/andes/Makefile b/arch/riscv/errata/andes/Makefile new file mode 100644 index 000000000000..2d644e19caef --- /dev/null +++ b/arch/riscv/errata/andes/Makefile @@ -0,0 +1 @@ +obj-y += errata.o diff --git a/arch/riscv/errata/andes/errata.c b/arch/riscv/errata/andes/errata.c new file mode 100644 index 000000000000..b7f3dbd04e58 --- /dev/null +++ b/arch/riscv/errata/andes/errata.c @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Erratas to be applied for Andes CPU cores + * + * Copyright (C) 2023 Renesas Electronics Corporation. + * + * Author: Lad Prabhakar + */ + +#include +#include +#include +#include +#include +#include + +#define ANDESTECH_AX45MP_MARCHID 0x8000000000008a45UL +#define ANDESTECH_AX45MP_MIMPID 0x500UL +#define ANDESTECH_SBI_EXT_ANDES 0x0900031E + +#define ANDES_SBI_EXT_IOCP_SW_WORKAROUND 1 + +static long ax45mp_iocp_sw_workaround(void) +{ + struct sbiret ret; + + /* + * ANDES_SBI_EXT_IOCP_SW_WORKAROUND SBI EXT checks if the IOCP is missing and + * cache is controllable only then CMO will be applied to the platform. + */ + ret = sbi_ecall(ANDESTECH_SBI_EXT_ANDES, ANDES_SBI_EXT_IOCP_SW_WORKAROUND, + 0, 0, 0, 0, 0, 0); + + return ret.error ? 0 : ret.value; +} + +static bool errata_probe_iocp(unsigned int stage, unsigned long arch_id, unsigned long impid) +{ + if (!IS_ENABLED(CONFIG_ERRATA_ANDES_CMO)) + return false; + + if (arch_id != ANDESTECH_AX45MP_MARCHID || impid != ANDESTECH_AX45MP_MIMPID) + return false; + + if (!ax45mp_iocp_sw_workaround()) + return false; + + /* Set this just to make core cbo code happy */ + riscv_cbom_block_size = 1; + riscv_noncoherent_supported(); + + return true; +} + +static void andes_errata_probe(unsigned int stage, unsigned long archid, unsigned long impid) +{ + /* + * In the absence of the I/O Coherency Port, access to certain peripherals + * requires vendor specific DMA handling. + */ + errata_probe_iocp(stage, archid, impid); +} + +void __init_or_module andes_errata_patch_func(struct alt_entry *begin, struct alt_entry *end, + unsigned long archid, unsigned long impid, + unsigned int stage) +{ + andes_errata_probe(stage, archid, impid); + + /* we have nothing to patch here ATM so just return back */ +} diff --git a/arch/riscv/include/asm/alternative.h b/arch/riscv/include/asm/alternative.h index 58ccd2f8cab7..3c2b59b25017 100644 --- a/arch/riscv/include/asm/alternative.h +++ b/arch/riscv/include/asm/alternative.h @@ -45,6 +45,9 @@ struct alt_entry { u32 patch_id; /* The patch ID (erratum ID or cpufeature ID) */ }; +void andes_errata_patch_func(struct alt_entry *begin, struct alt_entry *end, + unsigned long archid, unsigned long impid, + unsigned int stage); void sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end, unsigned long archid, unsigned long impid, unsigned int stage); diff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternative.c index 2354c69dc7d1..8a34e72c2b5e 100644 --- a/arch/riscv/kernel/alternative.c +++ b/arch/riscv/kernel/alternative.c @@ -42,6 +42,11 @@ static void __init_or_module riscv_fill_cpu_mfr_info(struct cpu_manufacturer_inf #endif switch (cpu_mfr_info->vendor_id) { +#ifdef CONFIG_ERRATA_ANDES + case ANDESTECH_VENDOR_ID: + cpu_mfr_info->patch_func = andes_errata_patch_func; + break; +#endif #ifdef CONFIG_ERRATA_SIFIVE case SIFIVE_VENDOR_ID: cpu_mfr_info->patch_func = sifive_errata_patch_func;