From patchwork Fri Mar 24 06:46:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hal Feng X-Patchwork-Id: 666725 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F142C6FD20 for ; Fri, 24 Mar 2023 06:47:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231346AbjCXGrG convert rfc822-to-8bit (ORCPT ); Fri, 24 Mar 2023 02:47:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54690 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230100AbjCXGrF (ORCPT ); Fri, 24 Mar 2023 02:47:05 -0400 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 357421514D; Thu, 23 Mar 2023 23:47:01 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 05E1024E207; Fri, 24 Mar 2023 14:46:53 +0800 (CST) Received: from EXMBX172.cuchost.com (172.16.6.92) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 24 Mar 2023 14:46:53 +0800 Received: from ubuntu.localdomain (113.72.145.117) by EXMBX172.cuchost.com (172.16.6.92) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 24 Mar 2023 14:46:52 +0800 From: Hal Feng To: , CC: Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Palmer Dabbelt" , Paul Walmsley , Albert Ou , Emil Renner Berthing , Hal Feng , Subject: [PATCH v1] riscv: dts: starfive: jh7110: Correct the properties of S7 core Date: Fri, 24 Mar 2023 14:46:51 +0800 Message-ID: <20230324064651.84670-1-hal.feng@starfivetech.com> X-Mailer: git-send-email 2.38.1 MIME-Version: 1.0 X-Originating-IP: [113.72.145.117] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX172.cuchost.com (172.16.6.92) X-YovoleRuleAgent: yovoleflag Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The S7 core has no L1 data cache and MMU, so delete some related properties. Signed-off-by: Hal Feng --- Hi, Conor, This is a correction for the S7 entry. This patch depends on patch [1]. [1] https://lore.kernel.org/all/20230320103750.60295-20-hal.feng@starfivetech.com/ --- arch/riscv/boot/dts/starfive/jh7110.dtsi | 9 --------- 1 file changed, 9 deletions(-) diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index d484ecdf93f7..4c5fdb905da8 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -20,21 +20,12 @@ cpus { S7_0: cpu@0 { compatible = "sifive,s7", "riscv"; reg = <0>; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <8192>; - d-tlb-sets = <1>; - d-tlb-size = <40>; device_type = "cpu"; i-cache-block-size = <64>; i-cache-sets = <64>; i-cache-size = <16384>; - i-tlb-sets = <1>; - i-tlb-size = <40>; - mmu-type = "riscv,sv39"; next-level-cache = <&ccache>; riscv,isa = "rv64imac_zba_zbb"; - tlb-split; status = "disabled"; cpu0_intc: interrupt-controller {