From patchwork Wed Mar 15 10:44:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Minda Chen X-Patchwork-Id: 663616 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5D5CBC6FD1D for ; Wed, 15 Mar 2023 10:44:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232420AbjCOKoX (ORCPT ); Wed, 15 Mar 2023 06:44:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42140 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232262AbjCOKoW (ORCPT ); Wed, 15 Mar 2023 06:44:22 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9A5C27C974; Wed, 15 Mar 2023 03:44:20 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 3CD1624E391; Wed, 15 Mar 2023 18:44:19 +0800 (CST) Received: from EXMBX071.cuchost.com (172.16.6.81) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 15 Mar 2023 18:44:19 +0800 Received: from ubuntu.localdomain (113.72.145.194) by EXMBX071.cuchost.com (172.16.6.81) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 15 Mar 2023 18:44:18 +0800 From: Minda Chen To: Emil Renner Berthing , Conor Dooley , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Pawel Laszczak , Greg Kroah-Hartman , Peter Chen , Roger Quadros , Philipp Zabel CC: , , , , , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Minda Chen" Subject: [PATCH v3 5/5] dts: usb: add StarFive JH7110 USB dts configuration. Date: Wed, 15 Mar 2023 18:44:11 +0800 Message-ID: <20230315104411.73614-6-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230315104411.73614-1-minda.chen@starfivetech.com> References: <20230315104411.73614-1-minda.chen@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [113.72.145.194] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX071.cuchost.com (172.16.6.81) X-YovoleRuleAgent: yovoleflag Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org USB Glue layer and Cadence USB subnode configuration, also includes USB and PCIe phy dts configuration. Signed-off-by: Minda Chen --- .../jh7110-starfive-visionfive-2.dtsi | 7 +++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 54 +++++++++++++++++++ 2 files changed, 61 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index a132debb9b53..c64476aebc1a 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -236,3 +236,10 @@ pinctrl-0 = <&uart0_pins>; status = "okay"; }; + +&usb0 { + status = "okay"; + usbdrd_cdns3: usb@0 { + dr_mode = "peripheral"; + }; +}; diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index f70a4ed47eb4..17722fd1be62 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -362,6 +362,60 @@ status = "disabled"; }; + usb0: usb@10100000 { + compatible = "starfive,jh7110-usb"; + clocks = <&stgcrg JH7110_STGCLK_USB0_LPM>, + <&stgcrg JH7110_STGCLK_USB0_STB>, + <&stgcrg JH7110_STGCLK_USB0_APB>, + <&stgcrg JH7110_STGCLK_USB0_AXI>, + <&stgcrg JH7110_STGCLK_USB0_UTMI_APB>; + clock-names = "lpm", "stb", "apb", "axi", "utmi_apb"; + resets = <&stgcrg JH7110_STGRST_USB0_PWRUP>, + <&stgcrg JH7110_STGRST_USB0_APB>, + <&stgcrg JH7110_STGRST_USB0_AXI>, + <&stgcrg JH7110_STGRST_USB0_UTMI_APB>; + starfive,stg-syscon = <&stg_syscon 0x4 0xc4 0x148 0x1f4>; + starfive,sys-syscon = <&sys_syscon 0x18>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x10100000 0x100000>; + + usbdrd_cdns3: usb@0 { + compatible = "cdns,usb3"; + reg = <0x0 0x10000>, + <0x10000 0x10000>, + <0x20000 0x10000>; + reg-names = "otg", "xhci", "dev"; + interrupts = <100>, <108>, <110>; + interrupt-names = "host", "peripheral", "otg"; + phys = <&usbphy0>; + phy-names = "cdns3,usb2-phy"; + maximum-speed = "super-speed"; + }; + }; + + usbphy0: phy@10200000 { + compatible = "starfive,jh7110-usb-phy"; + reg = <0x0 0x10200000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_USB_125M>, + <&stgcrg JH7110_STGCLK_USB0_APP_125>; + clock-names = "125m", "app_125"; + #phy-cells = <0>; + }; + + pciephy0: phy@10210000 { + compatible = "starfive,jh7110-pcie-phy"; + reg = <0x0 0x10210000 0x0 0x10000>; + #phy-cells = <0>; + }; + + pciephy1: phy@10220000 { + compatible = "starfive,jh7110-pcie-phy"; + reg = <0x0 0x10220000 0x0 0x10000>; + #phy-cells = <0>; + }; + stgcrg: clock-controller@10230000 { compatible = "starfive,jh7110-stgcrg"; reg = <0x0 0x10230000 0x0 0x10000>;