| Message ID | 20230315055813.94740-2-william.qiu@starfivetech.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | StarFive's SDIO/eMMC driver support | expand |
On 15/03/2023 06:58, William Qiu wrote: > Add documentation to describe StarFive System Controller Registers. > > Signed-off-by: William Qiu <william.qiu@starfivetech.com> > --- > .../soc/starfive/starfive,jh7110-syscon.yaml | 41 +++++++++++++++++++ > MAINTAINERS | 5 +++ > 2 files changed, 46 insertions(+) > create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml > > diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml > new file mode 100644 > index 000000000000..ae7f1d6916af > --- /dev/null > +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml > @@ -0,0 +1,41 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: StarFive JH7110 SoC system controller > + > +maintainers: > + - William Qiu <william.qiu@starfivetech.com> > + > +description: | > + The StarFive JH7110 SoC system controller provides register information such > + as offset, mask and shift to configure related modules such as MMC and PCIe. > + > +properties: > + compatible: > + items: > + - enum: > + - starfive,jh7110-aon-syscon > + - starfive,jh7110-stg-syscon > + - starfive,jh7110-sys-syscon > + - const: syscon Does not look like you tested the bindings. Please run `make dt_binding_check` (see Documentation/devicetree/bindings/writing-schema.rst for instructions). ... or your PLL clock controller was not tested. Best regards, Krzysztof
On 15/03/2023 06:58, William Qiu wrote: > Add documentation to describe StarFive System Controller Registers. > > Signed-off-by: William Qiu <william.qiu@starfivetech.com> > --- > .../soc/starfive/starfive,jh7110-syscon.yaml | 41 +++++++++++++++++++ > MAINTAINERS | 5 +++ > 2 files changed, 46 insertions(+) > create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml > > diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml > new file mode 100644 > index 000000000000..ae7f1d6916af > --- /dev/null > +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml > @@ -0,0 +1,41 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: StarFive JH7110 SoC system controller OK, I found the patch changing this. So basically you add knowingly incomplete bindings and a second later you fix them. Add complete bindings. Best regards, Krzysztof
On Mon, Mar 20, 2023 at 03:32:14PM +0800, William Qiu wrote: > >>> Does not look like you tested the bindings. Please run `make > >>> dt_binding_check` (see > >>> Documentation/devicetree/bindings/writing-schema.rst for instructions). > >>> > >>> ... or your PLL clock controller was not tested. > >>> > >>> Best regards, > >>> Krzysztof > >>> > >> Hi Krzysztof, > >> > >> I've already done`make dt_binding_check`, and get no error. So maybe PLL clock controller > >> was not tested which I didn't add in this patch series. And PLL clock controller belongs > >> to Xingyu Wu, I would tell him. > > > > What's confusing you do not allow here clock controller. > I'll add it then. What's the plan here William? Can you sort something out with Xingyu Wu so that the dt-binding is added in a complete manner? In the meantime, gonna drop this series as "Changes Requested" from patchwork. Cheers, Conor.
diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml new file mode 100644 index 000000000000..ae7f1d6916af --- /dev/null +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 SoC system controller + +maintainers: + - William Qiu <william.qiu@starfivetech.com> + +description: | + The StarFive JH7110 SoC system controller provides register information such + as offset, mask and shift to configure related modules such as MMC and PCIe. + +properties: + compatible: + items: + - enum: + - starfive,jh7110-aon-syscon + - starfive,jh7110-stg-syscon + - starfive,jh7110-sys-syscon + - const: syscon + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + syscon@10240000 { + compatible = "starfive,jh7110-stg-syscon", "syscon"; + reg = <0x10240000 0x1000>; + }; + +... diff --git a/MAINTAINERS b/MAINTAINERS index 958b7ec118b4..fdad60cc9f2e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19964,6 +19964,11 @@ S: Supported F: Documentation/devicetree/bindings/rng/starfive* F: drivers/char/hw_random/jh7110-trng.c +STARFIVE JH7110 SYSCON +M: William Qiu <william.qiu@starfivetech.com> +S: Supported +F: Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml + STATIC BRANCH/CALL M: Peter Zijlstra <peterz@infradead.org> M: Josh Poimboeuf <jpoimboe@kernel.org>
Add documentation to describe StarFive System Controller Registers. Signed-off-by: William Qiu <william.qiu@starfivetech.com> --- .../soc/starfive/starfive,jh7110-syscon.yaml | 41 +++++++++++++++++++ MAINTAINERS | 5 +++ 2 files changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml -- 2.34.1