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Mon, 13 Mar 2023 16:12:23 +0000 Received: from DB9PR03MB8847.eurprd03.prod.outlook.com ([fe80::dbcf:1089:3242:614e]) by DB9PR03MB8847.eurprd03.prod.outlook.com ([fe80::dbcf:1089:3242:614e%4]) with mapi id 15.20.6178.024; Mon, 13 Mar 2023 16:12:23 +0000 From: Sean Anderson To: Vinod Koul , Kishon Vijay Abraham I , linux-phy@lists.infradead.org Cc: Krzysztof Kozlowski , Rob Herring , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Camelia Alexandra Groza , Madalin Bucur , Bagas Sanjaya , Ioana Ciornei , linuxppc-dev@lists.ozlabs.org, Sean Anderson , Li Yang , Shawn Guo Subject: [PATCH v11 10/13] arm64: dts: ls1046ardb: Add serdes descriptions Date: Mon, 13 Mar 2023 12:11:34 -0400 Message-Id: <20230313161138.3598068-11-sean.anderson@seco.com> X-Mailer: git-send-email 2.35.1.1320.gc452695387.dirty In-Reply-To: <20230313161138.3598068-1-sean.anderson@seco.com> References: <20230313161138.3598068-1-sean.anderson@seco.com> X-ClientProxiedBy: BL1P221CA0013.NAMP221.PROD.OUTLOOK.COM (2603:10b6:208:2c5::11) To DB9PR03MB8847.eurprd03.prod.outlook.com (2603:10a6:10:3dd::13) MIME-Version: 1.0 X-MS-TrafficTypeDiagnostic: DB9PR03MB8847:EE_|AS8PR03MB7781:EE_|VI1EUR05FT052:EE_|AS8PR03MB8997:EE_ X-MS-Office365-Filtering-Correlation-Id: 789d0384-2c8a-4d7b-6733-08db23ddc201 X-TrendMicro-CAS-OUT-LOOP-IDENTIFIER: 656f966764b7fb185830381c646b41a1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; 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Ip=[20.160.56.87]; Helo=[inpost-eu.tmcas.trendmicro.com] X-MS-Exchange-CrossTenant-AuthSource: VI1EUR05FT052.eop-eur05.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR03MB8997 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds appropriate descriptions for the macs which use the SerDes. The 156.25MHz fixed clock is a crystal. The 100MHz clocks (there are actually 3) come from a Renesas 6V49205B at address 69 on i2c0. There is no driver for this device (and as far as I know all you can do with the 100MHz clocks is gate them), so I have chosen to model it as a single fixed clock. Note: the SerDes1 lane numbering for the LS1046A is *reversed*. This means that Lane A (what the driver thinks is lane 0) uses pins SD1_TX3_P/N. Signed-off-by: Sean Anderson --- (no changes since v10) Changes in v10: - Move serdes descriptions to SoC dtsi - Don't use /clocks - Use "descriptions" instead of "bindings" - Split off defconfig change into separate patch Changes in v9: - Fix name of phy mode node - phy-type -> fsl,phy Changes in v8: - Rename serdes phy handles to use _A, _B, etc. instead of _0, _1, etc. This should help remind readers that the numbering corresponds to the physical layout of the registers, and not the lane (pin) number. Changes in v6: - XGI.9 -> XFI.9 Changes in v4: - Convert to new bindings .../boot/dts/freescale/fsl-ls1046a-rdb.dts | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts index 07f6cc6e354a..0d6dcfd1630a 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts @@ -26,6 +26,24 @@ aliases { chosen { stdout-path = "serial0:115200n8"; }; + + clk_100mhz: clock-100mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + clk_156mhz: clock-156mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <156250000>; + }; +}; + +&serdes1 { + clocks = <&clk_100mhz>, <&clk_156mhz>; + clock-names = "ref0", "ref1"; + status = "okay"; }; &duart0 { @@ -140,21 +158,29 @@ ethernet@e6000 { ethernet@e8000 { phy-handle = <&sgmii_phy1>; phy-connection-type = "sgmii"; + phys = <&serdes1_B>; + phy-names = "serdes"; }; ethernet@ea000 { phy-handle = <&sgmii_phy2>; phy-connection-type = "sgmii"; + phys = <&serdes1_A>; + phy-names = "serdes"; }; ethernet@f0000 { /* 10GEC1 */ phy-handle = <&aqr106_phy>; phy-connection-type = "xgmii"; + phys = <&serdes1_D>; + phy-names = "serdes"; }; ethernet@f2000 { /* 10GEC2 */ phy-connection-type = "10gbase-r"; managed = "in-band-status"; + phys = <&serdes1_C>; + phy-names = "serdes"; }; mdio@fc000 {