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[93.34.89.197]) by smtp.googlemail.com with ESMTPSA id g12-20020a05600c310c00b003e209b45f6bsm1183981wmo.29.2023.03.09.14.37.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Mar 2023 14:37:57 -0800 (PST) From: Christian Marangi To: Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Heiner Kallweit , Russell King , Gregory Clement , Sebastian Hesselbarth , Andy Gross , Bjorn Andersson , Konrad Dybcio , Christian Marangi , John Crispin , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, Lee Jones , linux-leds@vger.kernel.org Subject: [net-next PATCH v2 01/14] net: dsa: qca8k: move qca8k_port_to_phy() to header Date: Thu, 9 Mar 2023 23:35:11 +0100 Message-Id: <20230309223524.23364-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230309223524.23364-1-ansuelsmth@gmail.com> References: <20230309223524.23364-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Move qca8k_port_to_phy() to qca8k header as it's useful for future reference in Switch LEDs module since the same logic is applied to get the right index of the switch port. Make it inline as it's simple function that just decrease the port. Signed-off-by: Christian Marangi --- drivers/net/dsa/qca/qca8k-8xxx.c | 15 --------------- drivers/net/dsa/qca/qca8k.h | 14 ++++++++++++++ 2 files changed, 14 insertions(+), 15 deletions(-) diff --git a/drivers/net/dsa/qca/qca8k-8xxx.c b/drivers/net/dsa/qca/qca8k-8xxx.c index 2f224b166bbb..8dfc5db84700 100644 --- a/drivers/net/dsa/qca/qca8k-8xxx.c +++ b/drivers/net/dsa/qca/qca8k-8xxx.c @@ -716,21 +716,6 @@ qca8k_phy_eth_command(struct qca8k_priv *priv, bool read, int phy, return ret; } -static u32 -qca8k_port_to_phy(int port) -{ - /* From Andrew Lunn: - * Port 0 has no internal phy. - * Port 1 has an internal PHY at MDIO address 0. - * Port 2 has an internal PHY at MDIO address 1. - * ... - * Port 5 has an internal PHY at MDIO address 4. - * Port 6 has no internal PHY. - */ - - return port - 1; -} - static int qca8k_mdio_busy_wait(struct mii_bus *bus, u32 reg, u32 mask) { diff --git a/drivers/net/dsa/qca/qca8k.h b/drivers/net/dsa/qca/qca8k.h index 03514f7a20be..4e48e4dd8b0f 100644 --- a/drivers/net/dsa/qca/qca8k.h +++ b/drivers/net/dsa/qca/qca8k.h @@ -422,6 +422,20 @@ struct qca8k_fdb { u8 mac[6]; }; +static inline u32 qca8k_port_to_phy(int port) +{ + /* From Andrew Lunn: + * Port 0 has no internal phy. + * Port 1 has an internal PHY at MDIO address 0. + * Port 2 has an internal PHY at MDIO address 1. + * ... + * Port 5 has an internal PHY at MDIO address 4. + * Port 6 has no internal PHY. + */ + + return port - 1; +} + /* Common setup function */ extern const struct qca8k_mib_desc ar8327_mib[]; extern const struct regmap_access_table qca8k_readable_table;