From patchwork Mon Mar 6 15:32:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 659498 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A874FC678D4 for ; Mon, 6 Mar 2023 15:34:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231326AbjCFPeh (ORCPT ); Mon, 6 Mar 2023 10:34:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59986 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230511AbjCFPeU (ORCPT ); Mon, 6 Mar 2023 10:34:20 -0500 Received: from mail-pl1-x635.google.com (mail-pl1-x635.google.com [IPv6:2607:f8b0:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E9C051FCC for ; Mon, 6 Mar 2023 07:33:42 -0800 (PST) Received: by mail-pl1-x635.google.com with SMTP id y11so10808567plg.1 for ; Mon, 06 Mar 2023 07:33:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678116819; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FSZTsxFvrcK51n2zirybFkKL1X1N/PtWqccn7VlsBoE=; b=CMF2lbQmJRo/nSmptNkmWK25ase0/6LStx4Q+kyliXRBjgF8nMVTfzYXz5xRwHy+Uv s+3dRUyQXoGOMT/psC+HQXqSQhG9talllgrxQD+Pnsuk4fPpHoJit7axA7AvnkB8btqk meyPqkjSgSQUrdMta+uFqNIbTvTXqJmPa13TztxaJWrSjFHQK/nEpyvbKStVlm42ieNM qn62Q4fQgXauS6szDyp+a6ckwa9dMilh4FrY9G/czNTeMtZtFReH8VaQmCi1KiUa3uFV wL/hqCcj4DM+qlvfnZ//SIAmRixAbI2MI9Iotny/xoGllPvYPbQEB+0iTg5XBQIaVkrS 65yg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678116819; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FSZTsxFvrcK51n2zirybFkKL1X1N/PtWqccn7VlsBoE=; b=EwoKt8EWdqRQ6D4+3E61Yu/tZD0UYhVLkNxmLu7s5fzqVSm8VahJLxv9tJXoc2lCHr iFg0VV+rlPWNtpB8BSz6D9f/pWvMjxV2gk37em8sLciS22/4lg3+3XdCkKiI/PehdT7j elV63wQ6wh7/mmoUR+7eyWmBpxIOTSWjWI339Wik3y32BGVN7bHe9XwooMrGw292DWkI KgcTOfBwuIFVIkkPw/F38k1hPQs88WE4I/ynStQ/DItWHeAzzM6rR/VL/aCUW7ru2CWt JqaQctyOEyDD65AMp3fgKSQS2Ixq2hkT/m3jebjwL/jj3MWJpi+CGE6/YKD2/EP/USqD ky8g== X-Gm-Message-State: AO0yUKW0fiZxgg31zlKzUetXNNQJ4E4Gos0d/pY2sZhxmgJquYQbeUMW 1+wtJpTcIkGlZnx31AJ5htqP X-Google-Smtp-Source: AK7set82IVvmz55x2cDlnkyaJV0+PnXaPQyULxNMeE+2vqBXVrH5YGgrlSTA2fAZcnEoKeHTkfXNCw== X-Received: by 2002:a17:903:2290:b0:19e:25b4:7740 with SMTP id b16-20020a170903229000b0019e25b47740mr13907805plh.28.1678116819521; Mon, 06 Mar 2023 07:33:39 -0800 (PST) Received: from localhost.localdomain ([59.97.52.140]) by smtp.gmail.com with ESMTPSA id kl4-20020a170903074400b0019a7c890c61sm6837430plb.252.2023.03.06.07.33.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Mar 2023 07:33:39 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH 14/19] PCI: qcom-ep: Rename "mmio" region to "mhi" Date: Mon, 6 Mar 2023 21:02:17 +0530 Message-Id: <20230306153222.157667-15-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230306153222.157667-1-manivannan.sadhasivam@linaro.org> References: <20230306153222.157667-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org As per Qualcomm's internal documentation, the name of the region is "mhi" and not "mmio". So let's rename it to follow the convention. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 38 +++++++++++------------ 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 19b32839ea26..a4983d3844f7 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -147,9 +147,9 @@ enum qcom_pcie_ep_link_status { * @pci: Designware PCIe controller struct * @parf: Qualcomm PCIe specific PARF register base * @elbi: Designware PCIe specific ELBI register base - * @mmio: MMIO register base + * @mhi: MHI register base * @perst_map: PERST regmap - * @mmio_res: MMIO region resource + * @mhi_res: MHI region resource * @core_reset: PCIe Endpoint core reset * @reset: PERST# GPIO * @wake: WAKE# GPIO @@ -168,9 +168,9 @@ struct qcom_pcie_ep { void __iomem *parf; void __iomem *elbi; - void __iomem *mmio; + void __iomem *mhi; struct regmap *perst_map; - struct resource *mmio_res; + struct resource *mhi_res; struct reset_control *core_reset; struct gpio_desc *reset; @@ -405,10 +405,10 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci) } /* - * The physical address of the MMIO region which is exposed as the BAR - * should be written to MHI BASE registers. + * The physical address of the MHI region which is exposed as the BAR + * should be written to PARF_MHI_BASE registers. */ - writel_relaxed(pcie_ep->mmio_res->start, + writel_relaxed(pcie_ep->mhi_res->start, pcie_ep->parf + PARF_MHI_BASE_ADDR_LOWER); writel_relaxed(0, pcie_ep->parf + PARF_MHI_BASE_ADDR_UPPER); @@ -477,16 +477,16 @@ static int qcom_pcie_ep_get_io_resources(struct platform_device *pdev, if (IS_ERR(pcie_ep->elbi)) return PTR_ERR(pcie_ep->elbi); - pcie_ep->mmio_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, - "mmio"); - if (!pcie_ep->mmio_res) { - dev_err(dev, "Failed to get mmio resource\n"); + pcie_ep->mhi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "mhi"); + if (!pcie_ep->mhi_res) { + dev_err(dev, "Failed to get mhi resource\n"); return -EINVAL; } - pcie_ep->mmio = devm_pci_remap_cfg_resource(dev, pcie_ep->mmio_res); - if (IS_ERR(pcie_ep->mmio)) - return PTR_ERR(pcie_ep->mmio); + pcie_ep->mhi = devm_pci_remap_cfg_resource(dev, pcie_ep->mhi_res); + if (IS_ERR(pcie_ep->mhi)) + return PTR_ERR(pcie_ep->mhi); syscon = of_parse_phandle(dev->of_node, "qcom,perst-regs", 0); if (!syscon) { @@ -674,19 +674,19 @@ static int qcom_pcie_ep_link_transition_count(struct seq_file *s, void *data) dev_get_drvdata(s->private); seq_printf(s, "L0s transition count: %u\n", - readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L0S)); + readl_relaxed(pcie_ep->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L0S)); seq_printf(s, "L1 transition count: %u\n", - readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L1)); + readl_relaxed(pcie_ep->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L1)); seq_printf(s, "L1.1 transition count: %u\n", - readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1)); + readl_relaxed(pcie_ep->mhi + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1)); seq_printf(s, "L1.2 transition count: %u\n", - readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2)); + readl_relaxed(pcie_ep->mhi + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2)); seq_printf(s, "L2 transition count: %u\n", - readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L2)); + readl_relaxed(pcie_ep->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L2)); return 0; }