diff mbox series

[14/19] PCI: qcom-ep: Rename "mmio" region to "mhi"

Message ID 20230306153222.157667-15-manivannan.sadhasivam@linaro.org
State New
Headers show
Series Qcom PCIe cleanups and improvements | expand

Commit Message

Manivannan Sadhasivam March 6, 2023, 3:32 p.m. UTC 
As per Qualcomm's internal documentation, the name of the region is "mhi"
and not "mmio". So let's rename it to follow the convention.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 drivers/pci/controller/dwc/pcie-qcom-ep.c | 38 +++++++++++------------
 1 file changed, 19 insertions(+), 19 deletions(-)

Comments

Krzysztof Kozlowski March 7, 2023, 8:19 a.m. UTC | #1 
On 06/03/2023 16:32, Manivannan Sadhasivam wrote:
> As per Qualcomm's internal documentation, the name of the region is "mhi"
> and not "mmio". So let's rename it to follow the convention.
> 
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---



>  
> @@ -477,16 +477,16 @@ static int qcom_pcie_ep_get_io_resources(struct platform_device *pdev,
>  	if (IS_ERR(pcie_ep->elbi))
>  		return PTR_ERR(pcie_ep->elbi);
>  
> -	pcie_ep->mmio_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> -							 "mmio");
> -	if (!pcie_ep->mmio_res) {
> -		dev_err(dev, "Failed to get mmio resource\n");
> +	pcie_ep->mhi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> +							 "mhi");

That's an ABI break. Patchset is also non-bisectable.

Best regards,
Krzysztof
diff mbox series

Patch

diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
index 19b32839ea26..a4983d3844f7 100644
--- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
+++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
@@ -147,9 +147,9 @@  enum qcom_pcie_ep_link_status {
  * @pci: Designware PCIe controller struct
  * @parf: Qualcomm PCIe specific PARF register base
  * @elbi: Designware PCIe specific ELBI register base
- * @mmio: MMIO register base
+ * @mhi: MHI register base
  * @perst_map: PERST regmap
- * @mmio_res: MMIO region resource
+ * @mhi_res: MHI region resource
  * @core_reset: PCIe Endpoint core reset
  * @reset: PERST# GPIO
  * @wake: WAKE# GPIO
@@ -168,9 +168,9 @@  struct qcom_pcie_ep {
 
 	void __iomem *parf;
 	void __iomem *elbi;
-	void __iomem *mmio;
+	void __iomem *mhi;
 	struct regmap *perst_map;
-	struct resource *mmio_res;
+	struct resource *mhi_res;
 
 	struct reset_control *core_reset;
 	struct gpio_desc *reset;
@@ -405,10 +405,10 @@  static int qcom_pcie_perst_deassert(struct dw_pcie *pci)
 	}
 
 	/*
-	 * The physical address of the MMIO region which is exposed as the BAR
-	 * should be written to MHI BASE registers.
+	 * The physical address of the MHI region which is exposed as the BAR
+	 * should be written to PARF_MHI_BASE registers.
 	 */
-	writel_relaxed(pcie_ep->mmio_res->start,
+	writel_relaxed(pcie_ep->mhi_res->start,
 		       pcie_ep->parf + PARF_MHI_BASE_ADDR_LOWER);
 	writel_relaxed(0, pcie_ep->parf + PARF_MHI_BASE_ADDR_UPPER);
 
@@ -477,16 +477,16 @@  static int qcom_pcie_ep_get_io_resources(struct platform_device *pdev,
 	if (IS_ERR(pcie_ep->elbi))
 		return PTR_ERR(pcie_ep->elbi);
 
-	pcie_ep->mmio_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
-							 "mmio");
-	if (!pcie_ep->mmio_res) {
-		dev_err(dev, "Failed to get mmio resource\n");
+	pcie_ep->mhi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+							 "mhi");
+	if (!pcie_ep->mhi_res) {
+		dev_err(dev, "Failed to get mhi resource\n");
 		return -EINVAL;
 	}
 
-	pcie_ep->mmio = devm_pci_remap_cfg_resource(dev, pcie_ep->mmio_res);
-	if (IS_ERR(pcie_ep->mmio))
-		return PTR_ERR(pcie_ep->mmio);
+	pcie_ep->mhi = devm_pci_remap_cfg_resource(dev, pcie_ep->mhi_res);
+	if (IS_ERR(pcie_ep->mhi))
+		return PTR_ERR(pcie_ep->mhi);
 
 	syscon = of_parse_phandle(dev->of_node, "qcom,perst-regs", 0);
 	if (!syscon) {
@@ -674,19 +674,19 @@  static int qcom_pcie_ep_link_transition_count(struct seq_file *s, void *data)
 				     dev_get_drvdata(s->private);
 
 	seq_printf(s, "L0s transition count: %u\n",
-		   readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L0S));
+		   readl_relaxed(pcie_ep->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L0S));
 
 	seq_printf(s, "L1 transition count: %u\n",
-		   readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L1));
+		   readl_relaxed(pcie_ep->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L1));
 
 	seq_printf(s, "L1.1 transition count: %u\n",
-		   readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1));
+		   readl_relaxed(pcie_ep->mhi + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1));
 
 	seq_printf(s, "L1.2 transition count: %u\n",
-		   readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2));
+		   readl_relaxed(pcie_ep->mhi + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2));
 
 	seq_printf(s, "L2 transition count: %u\n",
-		   readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L2));
+		   readl_relaxed(pcie_ep->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L2));
 
 	return 0;
 }