From patchwork Fri Feb 24 10:24:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ravi Gunasekaran X-Patchwork-Id: 657293 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D44FEC6FA9E for ; Fri, 24 Feb 2023 10:27:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230216AbjBXK1O (ORCPT ); Fri, 24 Feb 2023 05:27:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52284 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230105AbjBXK1M (ORCPT ); Fri, 24 Feb 2023 05:27:12 -0500 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D77E665330; Fri, 24 Feb 2023 02:26:37 -0800 (PST) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 31OAPDwr036191; Fri, 24 Feb 2023 04:25:13 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1677234313; bh=ox1KMDfAB1j8ke+6qURY/QgON8SqZToV88fIVZzRT+g=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=WD9ZNF+kQMhi8xeVURUwyYvDvTdjSd4xsFLzn2ibYCKnoPbRkUALMwhKHkrNlqD2Z rnm8imRZzRwZk6EieqYwT3DTswbtX6ikabTAkduT/EBKID/y/QsF068JSB480xSBsG crBqp3BzmikW+PVkG/XLwmWl2YuNKGEPufGBLTUU= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 31OAPDuV124418 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 24 Feb 2023 04:25:13 -0600 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Fri, 24 Feb 2023 04:25:13 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Fri, 24 Feb 2023 04:25:13 -0600 Received: from uda0500640.dal.design.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 31OAOcXi016652; Fri, 24 Feb 2023 04:25:10 -0600 From: Ravi Gunasekaran To: , , , , , , , , CC: , , Subject: [PATCH v11 8/8] arm64: dts: ti: k3-j721s2-common-proc-board: Enable PCIe Date: Fri, 24 Feb 2023 15:54:38 +0530 Message-ID: <20230224102438.6541-9-r-gunasekaran@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230224102438.6541-1-r-gunasekaran@ti.com> References: <20230224102438.6541-1-r-gunasekaran@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Aswath Govindraju x1 lane PCIe slot in the common processor board is enabled and connected to J721S2 SOM. Add PCIe DT node in common processor board to reflect the same. Reviewed-by: Siddharth Vadapalli Signed-off-by: Aswath Govindraju Signed-off-by: Vignesh Raghavendra Signed-off-by: Matt Ranostay Signed-off-by: Ravi Gunasekaran --- Changes from v10: * Removed Link tag from commit message Changes from v9: * No change Changes from v8: * No change Changes from v7: * No change Changes from v6: * Removed pcie_ep node update Changes from v5: * No change Changes from v4: * No change Changes from v3: * No change Changes from v2: * Patch newly added to the series arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index 76b420379645..b195f250891a 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -386,6 +386,14 @@ }; }; +&pcie1_rc { + status = "okay"; + reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <1>; +}; + &mcu_mcan0 { status = "okay"; pinctrl-names = "default";