From patchwork Fri Feb 24 10:24:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ravi Gunasekaran X-Patchwork-Id: 656331 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9286C6FA9D for ; Fri, 24 Feb 2023 10:27:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230137AbjBXK1N (ORCPT ); Fri, 24 Feb 2023 05:27:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52150 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230226AbjBXK1J (ORCPT ); Fri, 24 Feb 2023 05:27:09 -0500 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1035860D7B; Fri, 24 Feb 2023 02:26:29 -0800 (PST) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 31OAOwSd036044; Fri, 24 Feb 2023 04:24:58 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1677234298; bh=ag4cKjiWMK5uU1CgAhsPOjBT6cCQSA+U90GXtpT7im8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=nTtwmKhfjLlkU0+h0FK6kbDYK/Q6z67BfNuxawDfI9EPFm+n9bEpIrlmSf4qnnmRY 3LaaHziIG3kTSKuHaP+XgUuvz6jh/2Q/BIYx295wTcLv4zMuonjmJgYa6Jx+7YdVw4 67728qUlfOkWkhH+MgMhRHaccmAKCGoiO0UFuH/g= Received: from DLEE110.ent.ti.com (dlee110.ent.ti.com [157.170.170.21]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 31OAOwmB045684 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 24 Feb 2023 04:24:58 -0600 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Fri, 24 Feb 2023 04:24:57 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Fri, 24 Feb 2023 04:24:57 -0600 Received: from uda0500640.dal.design.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 31OAOcXe016652; Fri, 24 Feb 2023 04:24:54 -0600 From: Ravi Gunasekaran To: , , , , , , , , CC: , , Subject: [PATCH v11 4/8] arm64: dts: ti: k3-j721s2-common-proc-board: Enable SERDES0 Date: Fri, 24 Feb 2023 15:54:34 +0530 Message-ID: <20230224102438.6541-5-r-gunasekaran@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230224102438.6541-1-r-gunasekaran@ti.com> References: <20230224102438.6541-1-r-gunasekaran@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Aswath Govindraju Configure first lane to PCIe, the second lane to USB and the last two lanes to eDP. Also, add sub-nodes to SERDES0 DT node to represent SERDES0 is connected to PCIe. Signed-off-by: Aswath Govindraju Signed-off-by: Matt Ranostay Signed-off-by: Ravi Gunasekaran --- I had reviewed this patch in the v5 series [0]. Since I'm taking over upstreaming this series, I removed the self Reviewed-by tag. [0] - https://lore.kernel.org/all/71ce4ecd-2a50-c69d-28be-f1a8d769970e@ti.com/ Changes from v10: * Removed Link tag from commit message Changes from v9: * Enabled serdes related nodes Changes from v8: * No change Changes from v7: * No change Changes from v6: * No change Changes from v5: * Removed Cc tags from commit message Changes from v4: * No change Changes from v3: * No change Changes from v2: * No change Changes from v1: * No change .../dts/ti/k3-j721s2-common-proc-board.dts | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index a7aa6cf08acd..907f34ff22a5 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -9,6 +9,9 @@ #include "k3-j721s2-som-p0.dtsi" #include +#include +#include +#include / { compatible = "ti,j721s2-evm", "ti,j721s2"; @@ -296,6 +299,30 @@ phy-handle = <&phy0>; }; +&serdes_ln_ctrl { + idle-states = , , + , ; +}; + +&serdes_refclk { + clock-frequency = <100000000>; +}; + +&serdes_wiz0 { + status = "okay"; +}; + +&serdes0 { + status = "okay"; + serdes0_pcie_link: phy@0 { + reg = <0>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz0 1>; + }; +}; + &mcu_mcan0 { status = "okay"; pinctrl-names = "default";