From patchwork Fri Feb 24 10:24:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ravi Gunasekaran X-Patchwork-Id: 656330 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CDB87C61DA3 for ; Fri, 24 Feb 2023 10:27:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230262AbjBXK1V (ORCPT ); Fri, 24 Feb 2023 05:27:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52498 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230250AbjBXK1S (ORCPT ); Fri, 24 Feb 2023 05:27:18 -0500 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 09C0A58B41; Fri, 24 Feb 2023 02:26:43 -0800 (PST) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 31OAOk5V118593; Fri, 24 Feb 2023 04:24:46 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1677234287; bh=tcGeFFclS1r13HGoMopW6myyLPIqHj37LDYBgSWA4GY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=LEvVIa+uef9eh5YmA44Ez7i6ewWXpT540rQ4huUM2zEfuMEljafI/QQEMS0/rOst9 B5JXChcEqPQOppjhZFXgmZWQwbZmUYe/MkrrL9x712q2kmp2fg2eLeKI8DcGv/XUlr AQmwH5mLtuEwK3lfb0uiHyCoitsWtA2UFJJck+ow= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 31OAOkYN124074 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 24 Feb 2023 04:24:46 -0600 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Fri, 24 Feb 2023 04:24:46 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Fri, 24 Feb 2023 04:24:46 -0600 Received: from uda0500640.dal.design.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 31OAOcXb016652; Fri, 24 Feb 2023 04:24:43 -0600 From: Ravi Gunasekaran To: , , , , , , , , CC: , , Subject: [PATCH v11 1/8] arm64: dts: ti: k3-j721s2-main: Add support for USB Date: Fri, 24 Feb 2023 15:54:31 +0530 Message-ID: <20230224102438.6541-2-r-gunasekaran@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230224102438.6541-1-r-gunasekaran@ti.com> References: <20230224102438.6541-1-r-gunasekaran@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Aswath Govindraju Add support for single instance of USB 3.0 controller in J721S2 SoC. Signed-off-by: Aswath Govindraju Signed-off-by: Matt Ranostay Signed-off-by: Ravi Gunasekaran --- I had reviewed this patch in the v5 series [0]. Since I'm taking over upstreaming this series, I removed the self Reviewed-by tag. [0] - https://lore.kernel.org/all/134c28a0-2d49-549c-dc8d-0887d8fd29c3@ti.com/ Changes from v10: * Fixed dtbs warnings by adding "reg" property to the mux-controller nodes. * Documented the reason for disabling the nodes by default. * Removed Link tag from commit message Changes from v9: * Disabled USB nodes by default in common DT file. Changes from v8: * Updated mux-controller node name to fix dtbs warnings. Changes from v7: * No change Changes from v6: * No change Changes from v5: * No change Changes from v4: * Removed Cc tags from commit message Changes from v3: * No change Changes from v2: * No change Changes from v1: * Updated mux-controller node name. arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 57 ++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index 8915132efcc1..c6b5ffbcbc73 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -26,6 +26,21 @@ }; }; + scm_conf: syscon@104000 { + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; + reg = <0x00 0x00104000 0x00 0x18000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0x00104000 0x18000>; + + usb_serdes_mux: mux-controller@0 { + compatible = "mmio-mux"; + reg = <0x0 0x4>; + #mux-control-cells = <1>; + mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ + }; + }; + gic500: interrupt-controller@1800000 { compatible = "arm,gic-v3"; #address-cells = <2>; @@ -745,6 +760,48 @@ }; }; + usbss0: cdns-usb@4104000 { + compatible = "ti,j721e-usb"; + reg = <0x00 0x04104000 0x00 0x100>; + clocks = <&k3_clks 360 16>, <&k3_clks 360 15>; + clock-names = "ref", "lpm"; + assigned-clocks = <&k3_clks 360 16>; /* USB2_REFCLK */ + assigned-clock-parents = <&k3_clks 360 17>; + power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-coherent; + + /* + * Disable the node by default in the common include file. + * And enable it in the board specific DT file where the + * pinmux property is added. + */ + status = "disabled"; + + usb0: usb@6000000 { + compatible = "cdns,usb3"; + reg = <0x00 0x06000000 0x00 0x10000>, + <0x00 0x06010000 0x00 0x10000>, + <0x00 0x06020000 0x00 0x10000>; + reg-names = "otg", "xhci", "dev"; + interrupts = , + , + ; + interrupt-names = "host", "peripheral", "otg"; + maximum-speed = "super-speed"; + dr_mode = "otg"; + + /* + * Disable the node by default in the common include + * file. And enable it in the board specific DT file + * where the pinmux property is added. + */ + status = "disabled"; + }; + }; + main_mcan0: can@2701000 { compatible = "bosch,m_can"; reg = <0x00 0x02701000 0x00 0x200>,