From patchwork Thu Feb 23 12:06:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 657347 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 16388C61DA4 for ; Thu, 23 Feb 2023 12:07:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233999AbjBWMH0 (ORCPT ); Thu, 23 Feb 2023 07:07:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33686 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233708AbjBWMHI (ORCPT ); Thu, 23 Feb 2023 07:07:08 -0500 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3AEB555C38 for ; Thu, 23 Feb 2023 04:06:59 -0800 (PST) Received: by mail-lf1-x133.google.com with SMTP id r27so11391051lfe.10 for ; Thu, 23 Feb 2023 04:06:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=SfCORXPcL+h5lz5tUo1IeF01Q1PtyLtEsTTqCRkpbtc=; b=m1hEhlxagvqU+X4OQkEzMFcRfrqsr1fXwx/quu8B/Mi64Ed4HE3d88kofupNBQ9VLC 8g4VX/eMCm4p811Oqojx7WoO6bqtxIX/5dc1W4uykUFOoh30sApoanGTZqugnJ/mUEPO prmDL+d/pefj9Y1GUq625J9mZ3trvIkSllUW1XuZvD6JZg5y+ji4RGH1r8CauPsY8FnG EN59tWb2pbu+IqOxf/l6X8V2HnBlz0IzWzaDgnvuU6GJ9NtlJSGXJqYsfbHQtfCJtjOT P4PHXntQoJJjY6A9JcTWjDs1wagfLPF9C8uodBqRMsahOF/dpi4wakY3kWI6lXv8zzTd 6owA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SfCORXPcL+h5lz5tUo1IeF01Q1PtyLtEsTTqCRkpbtc=; b=b/9Eu1W7p6Q/brxir1UY9mGWpD4M1pU7rwHzJjh4+n/Dx23kp9e+xNUDWBD56xDtai 2W0UaOQsNWL/6JXwmWCzMCchJyCs8fYwdwbsSQSM4YTh5xXVFAeCRa6MmtO5CRoSM6PC gdGN39Xg65gSOWjT+ZBFUbuEBicb6Z7HRgkoTOayRMqPbYHSBczUnrdpAAroH+bJo9ys lgsp29s+qVrnss5ILhagH+srJccptJAamYOOC6iOYfAN0nPUZpZnlSWeyWAjLoUn4kxE kmWB5uPATp2JgfD7b4Y3/A/dksKb5hHam+DBEtPNig7QDHxF6mg33gPna/n3kqRhdo5C LDIw== X-Gm-Message-State: AO0yUKWkxUhEVRY+RNCPo7fu0mbnHA5tNDiwa3Os9PMe57W73+yXQ4kn vZJptLSvJGJde3tG74HqqwbKHA== X-Google-Smtp-Source: AK7set96Z0IikrlkjsFKvBy1HZU/L1ayL/YAvTC+3zS7v0b3E+52quOUWToH9WOZeKzVGV5DJLGivg== X-Received: by 2002:a05:6512:3f05:b0:4d8:86c1:4771 with SMTP id y5-20020a0565123f0500b004d886c14771mr3926322lfa.6.1677154017193; Thu, 23 Feb 2023 04:06:57 -0800 (PST) Received: from [192.168.1.101] (abxi151.neoplus.adsl.tpnet.pl. [83.9.2.151]) by smtp.gmail.com with ESMTPSA id h23-20020a2ea497000000b0029599744c02sm414838lji.75.2023.02.23.04.06.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Feb 2023 04:06:56 -0800 (PST) From: Konrad Dybcio Date: Thu, 23 Feb 2023 13:06:42 +0100 Subject: [PATCH v3 08/15] drm/msm/a6xx: Add support for A619_holi MIME-Version: 1.0 Message-Id: <20230223-topic-gmuwrapper-v3-8-5be55a336819@linaro.org> References: <20230223-topic-gmuwrapper-v3-0-5be55a336819@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v3-0-5be55a336819@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1677154003; l=5033; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=MYCmAcgrqxscwupX3STzV6AcutfLVBuoAIsGBJpJO2M=; b=f5CIErDJ6neIbmSo2eANhxIuE4KTjLQCvCxu+O+2Np2QaAR+SuynfgZ/ISxfq9kiOEdip8FhUPkO SvOltBL7BwHPRyZXBGMJVawNyxJZEo9UJ9geSsVCfUMhap6gXx6J X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org A619_holi is a GMU-less variant of the already-supported A619 GPU. It's present on at least SM4350 (holi) and SM6375 (blair). No mesa changes are required. Add the required kernel-side support for it. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 43 +++++++++++++++++++++++++-------- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 ++++ 2 files changed, 38 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index a8b727b82389..0859a6f463f9 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -614,14 +614,16 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) return; /* Disable SP clock before programming HWCG registers */ - if (!adreno_has_gmu_wrapper(adreno_gpu)) + if (!adreno_has_gmu_wrapper(adreno_gpu) || + adreno_is_a619_holi(adreno_gpu)) gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0); for (i = 0; (reg = &adreno_gpu->info->hwcg[i], reg->offset); i++) gpu_write(gpu, reg->offset, state ? reg->value : 0); /* Enable SP clock */ - if (!adreno_has_gmu_wrapper(adreno_gpu)) + if (!adreno_has_gmu_wrapper(adreno_gpu) || + adreno_is_a619_holi(adreno_gpu)) gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1); gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0); @@ -814,8 +816,8 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) if (adreno_is_a618(adreno_gpu)) return; - if (adreno_is_a619(adreno_gpu)) { - /* HBB = 14 */ + if (adreno_is_a619(adreno_gpu) && !adreno_is_a619_holi(adreno_gpu)) { + /* HBB = 14 on A619, default 0 on A619_holi */ hbb_lo = 1; } @@ -1029,7 +1031,12 @@ static int hw_init(struct msm_gpu *gpu) } /* Clear GBIF halt in case GX domain was not collapsed */ - if (a6xx_has_gbif(adreno_gpu)) { + if (adreno_is_a619_holi(adreno_gpu)) { + gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); + gpu_write(gpu, 0x18, 0); + /* Let's make extra sure that the GPU can access the memory.. */ + mb(); + } else if (a6xx_has_gbif(adreno_gpu)) { gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 0); /* Let's make extra sure that the GPU can access the memory.. */ @@ -1038,6 +1045,9 @@ static int hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0); + if (adreno_is_a619_holi(adreno_gpu)) + a6xx_sptprac_enable(gmu); + /* * Disable the trusted memory range - we don't actually supported secure * memory rendering at this point in time and we don't want to block off @@ -1315,7 +1325,8 @@ static void a6xx_dump(struct msm_gpu *gpu) #define GBIF_CLIENT_HALT_MASK BIT(0) #define GBIF_ARB_HALT_MASK BIT(1) #define VBIF_RESET_ACK_TIMEOUT 100 -#define VBIF_RESET_ACK_MASK 0x00f0 +#define VBIF_RESET_ACK_MASK 0xF0 +#define GPR0_GBIF_HALT_REQUEST 0x1E0 static void a6xx_recover(struct msm_gpu *gpu) { @@ -1372,10 +1383,16 @@ static void a6xx_recover(struct msm_gpu *gpu) /* Software-reset the GPU */ if (adreno_has_gmu_wrapper(adreno_gpu)) { - /* Halt the GX side of GBIF */ - gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, GBIF_GX_HALT_MASK); - spin_until(gpu_read(gpu, REG_A6XX_RBBM_GBIF_HALT_ACK) & - GBIF_GX_HALT_MASK); + if (adreno_is_a619_holi(adreno_gpu)) { + gpu_write(gpu, 0x18, GPR0_GBIF_HALT_REQUEST); + spin_until((gpu_read(gpu, REG_A6XX_RBBM_VBIF_GX_RESET_STATUS) & + (VBIF_RESET_ACK_MASK)) == VBIF_RESET_ACK_MASK); + } else { + /* Halt the GX side of GBIF */ + gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, GBIF_GX_HALT_MASK); + spin_until(gpu_read(gpu, REG_A6XX_RBBM_GBIF_HALT_ACK) & + GBIF_GX_HALT_MASK); + } /* Halt new client requests on GBIF */ gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK); @@ -1797,6 +1814,9 @@ static int a6xx_pm_resume(struct msm_gpu *gpu) if (ret) goto err; + if (adreno_is_a619_holi(adreno_gpu)) + a6xx_sptprac_enable(gmu); + err: mutex_unlock(&a6xx_gpu->gmu.lock); @@ -1851,6 +1871,9 @@ static int a6xx_pm_suspend(struct msm_gpu *gpu) mutex_lock(&a6xx_gpu->gmu.lock); + if (adreno_is_a619_holi(adreno_gpu)) + a6xx_sptprac_disable(gmu); + clk_disable_unprepare(gpu->ebi1_clk); clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 2c0f0ef094cb..92ece15ec7d8 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -252,6 +252,11 @@ static inline int adreno_is_a619(struct adreno_gpu *gpu) return gpu->revn == 619; } +static inline int adreno_is_a619_holi(struct adreno_gpu *gpu) +{ + return adreno_is_a619(gpu) && adreno_has_gmu_wrapper(gpu); +} + static inline int adreno_is_a630(struct adreno_gpu *gpu) { return gpu->revn == 630;