From patchwork Mon Feb 20 11:14:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ravi Gunasekaran X-Patchwork-Id: 655194 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23ED9C05027 for ; Mon, 20 Feb 2023 11:15:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231713AbjBTLPR (ORCPT ); Mon, 20 Feb 2023 06:15:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40032 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231790AbjBTLPL (ORCPT ); Mon, 20 Feb 2023 06:15:11 -0500 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0CA74196BC; Mon, 20 Feb 2023 03:14:49 -0800 (PST) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 31KBEirQ121343; Mon, 20 Feb 2023 05:14:45 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1676891685; bh=+ssO23ZnbPVTq5KM+ul2R8Prj2eZElnOjpVh7tIaxsg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=HNoOstnGsdVkbbp1hMi2fLBl2DrSC82lqvbmwpybA7H1BkKyd+OvJ6bMGiZ9inMNa iLiwX44FVqUzZjIGm9F1VMF1X2DBzYED2IS5qaoowYk5yMKR0FxeamSC2vb+r8kzaH AJxh0JoUt83sXDFsJF1sxzpGtsp6bIAKu0qY/ric= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 31KBEiws080699 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 20 Feb 2023 05:14:44 -0600 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Mon, 20 Feb 2023 05:14:44 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Mon, 20 Feb 2023 05:14:44 -0600 Received: from uda0500640.dal.design.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 31KBE98A068490; Mon, 20 Feb 2023 05:14:41 -0600 From: Ravi Gunasekaran To: , , , , , , , CC: , , Subject: [PATCH v9 9/9] arm64: dts: ti: k3-j721s2-common-proc-board: Enable PCIe Date: Mon, 20 Feb 2023 16:44:08 +0530 Message-ID: <20230220111408.9476-10-r-gunasekaran@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230220111408.9476-1-r-gunasekaran@ti.com> References: <20230220111408.9476-1-r-gunasekaran@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Aswath Govindraju x1 lane PCIe slot in the common processor board is enabled and connected to J721S2 SOM. Add PCIe DT node in common processor board to reflect the same. Reviewed-by: Siddharth Vadapalli Signed-off-by: Aswath Govindraju Signed-off-by: Vignesh Raghavendra Signed-off-by: Matt Ranostay Link: https://lore.kernel.org/r/20221122101616.770050-9-mranostay@ti.com Signed-off-by: Ravi Gunasekaran --- arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index 0503e690cfaf..561d70cdee9b 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -374,6 +374,13 @@ }; }; +&pcie1_rc { + reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <1>; +}; + &mcu_mcan0 { status = "okay"; pinctrl-names = "default";