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Mon, 25 Sep 2023 11:17:53 -0700 (PDT) Received: from [127.0.1.1] ([93.5.22.158]) by smtp.googlemail.com with ESMTPSA id j26-20020a170906831a00b00997d7aa59fasm6793962ejx.14.2023.09.25.11.17.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Sep 2023 11:17:52 -0700 (PDT) From: Alexandre Mergnat Date: Mon, 25 Sep 2023 20:17:41 +0200 Subject: [PATCH v6 7/7] arm64: dts: mediatek: add iommu support for mt8365 SoC Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20230207-iommu-support-v6-7-24453c8625b3@baylibre.com> References: <20230207-iommu-support-v6-0-24453c8625b3@baylibre.com> In-Reply-To: <20230207-iommu-support-v6-0-24453c8625b3@baylibre.com> To: Yong Wu , Krzysztof Kozlowski , Rob Herring , Matthias Brugger , AngeloGioacchino Del Regno , Krzysztof Kozlowski , Conor Dooley Cc: linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Alexandre Mergnat X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Add iommu support in the SoC DTS using the 4 local arbiters (LARBs) Reviewed-by: Yong Wu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Alexandre Mergnat --- arch/arm64/boot/dts/mediatek/mt8365.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi index afcfa1dd242e..24581f7410aa 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -471,6 +471,14 @@ sysirq: interrupt-controller@10200a80 { reg = <0 0x10200a80 0 0x20>; }; + iommu: iommu@10205000 { + compatible = "mediatek,mt8365-m4u"; + reg = <0 0x10205000 0 0x1000>; + interrupts = ; + mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, <&larb3>; + #iommu-cells = <1>; + }; + infracfg_nao: infracfg@1020e000 { compatible = "mediatek,mt8365-infracfg", "syscon"; reg = <0 0x1020e000 0 0x1000>;