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Mon, 25 Sep 2023 11:17:49 -0700 (PDT) Received: from [127.0.1.1] ([93.5.22.158]) by smtp.googlemail.com with ESMTPSA id j26-20020a170906831a00b00997d7aa59fasm6793962ejx.14.2023.09.25.11.17.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Sep 2023 11:17:48 -0700 (PDT) From: Alexandre Mergnat Date: Mon, 25 Sep 2023 20:17:38 +0200 Subject: [PATCH v6 4/7] arm64: dts: mediatek: add power domain support for mt8365 SoC Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20230207-iommu-support-v6-4-24453c8625b3@baylibre.com> References: <20230207-iommu-support-v6-0-24453c8625b3@baylibre.com> In-Reply-To: <20230207-iommu-support-v6-0-24453c8625b3@baylibre.com> To: Yong Wu , Krzysztof Kozlowski , Rob Herring , Matthias Brugger , AngeloGioacchino Del Regno , Krzysztof Kozlowski , Conor Dooley Cc: linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Alexandre Mergnat X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4724; i=amergnat@baylibre.com; h=from:subject:message-id; bh=gs34qYbpVZeuz1fNLXc7xbInSDTbehayNY8q/g3uDQE=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBlEc7FTl0niKBNPCGJeVVRHlwIKP3BNxOpKFNI/WZ3 aOVdKlaJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCZRHOxQAKCRArRkmdfjHURdtSEA CatxECkwOq3wcsJTPGcFEU7RSbi/wBwvLt7VskfT0wIhq1yCI+pjsjzrz9oNGZipCxfnMHNlFBgdyZ WOOHDr/BpKDfM1yF/seseJVXGCX0x1xT7G85YWFG/LIlkNVHXCYa/UryKUbXPF22L51DC9gAA0R5qD 2w7PMEfH4THcTCu6515DnrKwohESLR/qzv0cLyDleR0/Ro4TxgO8nZXk2QggcZxNphC5FVK8C0OqBY oC6fyvk5/SevsuAjkxuP2RSw9WkolLHdMFFFEKKwdo8Xq0dl1yF/jjB4pcTaB6bINLf9Kcrvx6uoL4 YO/1RbmWQ0sXmQNt5cHwF5OSxiYGFP6p398uo/RpSzSzr0AJRMS6jg45iIMNVuYhWqHE8LiWA08KtJ +7nWiLl8pFpOcW4AbK8w+mVN/SNSAYU5nFxq34y/NPpgCwSD5oJgBknXodsXkYfJ/uP/iYcsZQAsRE QBYzKJu9L7Z5hHyogwLGDi/qy3SkE+8+oaXZfxTnQoLySs9SwYTjjxDw+rNDsBLaCtTcu5447y44my JVCuvhGX6Zv0xBK1jzB50JOMDyHCi1O4622FblOwHQpyVSW1LgqKlraU4rTQmUxFQEzBpjKd5u01Au wMfOrTbGpDQKp7BjsIOt4WDTAqI6KVA8c7faZwV3i+alLzaGBd7oG3pvXKdQ== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net The following power domain are added to the SoC dts: - MM (MultiMedia) - CONN (Connectivity) - MFG (MFlexGraphics) - Audio - Cam (Camera) - DSP (Digital Signal Processor) - Vdec (Video decoder) - Venc (Video encoder) - APU (AI Processor Unit) Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Alexandre Mergnat --- arch/arm64/boot/dts/mediatek/mt8365.dtsi | 110 +++++++++++++++++++++++++++++++ 1 file changed, 110 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi index c3ad7cbc89ab..c2f88d153dee 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include / { compatible = "mediatek,mt8365"; @@ -298,6 +299,115 @@ syscfg_pctl: syscfg-pctl@10005000 { reg = <0 0x10005000 0 0x1000>; }; + scpsys: syscon@10006000 { + compatible = "mediatek,mt8365-syscfg", "syscon", "simple-mfd"; + reg = <0 0x10006000 0 0x1000>; + #power-domain-cells = <1>; + + /* System Power Manager */ + spm: power-controller { + compatible = "mediatek,mt8365-power-controller"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + /* power domains of the SoC */ + power-domain@MT8365_POWER_DOMAIN_MM { + reg = ; + clocks = <&topckgen CLK_TOP_MM_SEL>, + <&mmsys CLK_MM_MM_SMI_COMMON>, + <&mmsys CLK_MM_MM_SMI_COMM0>, + <&mmsys CLK_MM_MM_SMI_COMM1>, + <&mmsys CLK_MM_MM_SMI_LARB0>; + clock-names = "mm", "mm-0", "mm-1", + "mm-2", "mm-3"; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + mediatek,infracfg-nao = <&infracfg_nao>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@MT8365_POWER_DOMAIN_CAM { + reg = ; + clocks = <&camsys CLK_CAM_LARB2>, + <&camsys CLK_CAM_SENIF>, + <&camsys CLK_CAMSV0>, + <&camsys CLK_CAMSV1>, + <&camsys CLK_CAM_FDVT>, + <&camsys CLK_CAM_WPE>; + clock-names = "cam-0", "cam-1", + "cam-2", "cam-3", + "cam-4", "cam-5"; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + }; + + power-domain@MT8365_POWER_DOMAIN_VDEC { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT8365_POWER_DOMAIN_VENC { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT8365_POWER_DOMAIN_APU { + reg = ; + clocks = <&infracfg CLK_IFR_APU_AXI>, + <&apu CLK_APU_IPU_CK>, + <&apu CLK_APU_AXI>, + <&apu CLK_APU_JTAG>, + <&apu CLK_APU_IF_CK>, + <&apu CLK_APU_EDMA>, + <&apu CLK_APU_AHB>; + clock-names = "apu", "apu-0", + "apu-1", "apu-2", + "apu-3", "apu-4", + "apu-5"; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + }; + }; + + power-domain@MT8365_POWER_DOMAIN_CONN { + reg = ; + clocks = <&topckgen CLK_TOP_CONN_32K>, + <&topckgen CLK_TOP_CONN_26M>; + clock-names = "conn", "conn1"; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + }; + + power-domain@MT8365_POWER_DOMAIN_MFG { + reg = ; + clocks = <&topckgen CLK_TOP_MFG_SEL>; + clock-names = "mfg"; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + }; + + power-domain@MT8365_POWER_DOMAIN_AUDIO { + reg = ; + clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>, + <&infracfg CLK_IFR_AUDIO>, + <&infracfg CLK_IFR_AUD_26M_BK>; + clock-names = "audio", "audio1", "audio2"; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + }; + + power-domain@MT8365_POWER_DOMAIN_DSP { + reg = ; + clocks = <&topckgen CLK_TOP_DSP_SEL>, + <&topckgen CLK_TOP_DSP_26M>; + clock-names = "dsp", "dsp1"; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + }; + }; + }; + watchdog: watchdog@10007000 { compatible = "mediatek,mt8365-wdt", "mediatek,mt6589-wdt"; reg = <0 0x10007000 0 0x100>;