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[90.63.244.31]) by smtp.googlemail.com with ESMTPSA id o13-20020a5d670d000000b002c8476dde7asm12657607wru.114.2023.03.07.05.46.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Mar 2023 05:46:41 -0800 (PST) From: Alexandre Mergnat Date: Tue, 07 Mar 2023 14:46:31 +0100 Subject: [PATCH 6/6] arm64: dts: mediatek: add iommu support for mt8365 SoC MIME-Version: 1.0 Message-Id: <20230207-iommu-support-v1-6-4f0c81fd52c1@baylibre.com> References: <20230207-iommu-support-v1-0-4f0c81fd52c1@baylibre.com> In-Reply-To: <20230207-iommu-support-v1-0-4f0c81fd52c1@baylibre.com> To: Krzysztof Kozlowski , Rob Herring , Matthias Brugger , Yong Wu , Krzysztof Kozlowski , AngeloGioacchino Del Regno Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, Alexandre Mergnat , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=969; i=amergnat@baylibre.com; h=from:subject:message-id; bh=r7GkCkHYdd12Bt7dFmR03rMsJTMhNcidJ4FTEsGU2Yk=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBkB0A7CDFByNdlviQNt8kE2Cw9wrh0z75ZvZpOdikX kFOxAUGJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCZAdAOwAKCRArRkmdfjHURYKWD/ 94UAAbnpoF14YAwi4BJcFcufFpJmrKQxWeHQnzyW4ELK2wbH5OUOcak4XA4TcLSl6Re4TlCu8DQt4w UFvzMALTpLAF1FHEXQ+Z4bQJ5Ejcg6vsv3EJogtvguC/TBwl6AsJdrEU5QBaULWNdOJ+zRsGAW+Nmy PXDGOcIhPUFMoEU1TOoQiLhECf6n+/JXr+lUskFw5+nSnUtNmW7UgB80CHgbkhznncOdoVaGhSO2n7 8XIVHMWUyfrcNOCUElq+HzYFjo66T9Mc/EyoEgBFdKJA6kxzfOnigv5SxTRGhYa5wOLp/8aQhUVNdw bGzseWg8NbAas+ViGqwB4J/+BKCvLLWbFcmccTg6WZ+L2MeLqO6iLwMrz7ejVOIhVawn9nMvU0OUjY MYDM0V/qS/OMaeD3Ecj5NRBKWIKD2H5tkgVg5NFEBPsVrqx/85DLfIQzNuTorMzniJTzlxFy5a8JO6 h1uV90ov460FnvMbPkuEiBrtrCyNdVHM+TGtlifHNIVevMZL6u9pwBsjLQspfH5giaiRzj4XvmijZW SeulrzQrnKx0FUUV7r0ATeH1BZmuQeSakFevKCi7cUoxxZldlKL7h5FO5m9CqUmA1BZgtknWttAIEv JFgNMvi/ylZqDx4vPPib+Yq//xdlLY1pMP7xolKZYzFf03OxSA7+OKiWiVcA== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add iommu support in the SoC DTS using the 4 local arbiters (LARBs) Signed-off-by: Alexandre Mergnat --- arch/arm64/boot/dts/mediatek/mt8365.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi index db0b897f58bb..c713471c59dc 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -456,6 +456,14 @@ sysirq: interrupt-controller@10200a80 { reg = <0 0x10200a80 0 0x20>; }; + iommu: iommu@10205000 { + compatible = "mediatek,mt8365-m4u"; + reg = <0 0x10205000 0 0x1000>; + interrupts = ; + mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, <&larb3>; + #iommu-cells = <1>; + }; + infracfg_nao: infracfg@1020e000 { compatible = "mediatek,mt8365-infracfg", "syscon"; reg = <0 0x1020e000 0 0x1000>;