| Message ID | 20230202104452.299048-6-krzysztof.kozlowski@linaro.org |
|---|---|
| State | Accepted |
| Commit | 5c7069712c9be01d1bf9061a7ef5ce78df0af0a5 |
| Headers | show |
| Series | pinctrl/ARM/arm64: qcom: correct TLMM gpio-ranges and GPIO pin names | expand |
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml index add3c7e64520..a40175258495 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml @@ -55,7 +55,7 @@ $defs: List of gpio pins affected by the properties specified in this subnode. items: oneOf: - - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-6])$" + - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-7])$" - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ] minItems: 1 maxItems: 36
The SDX55 TLMM pin controller has GPIOs 0-107, so narrow the pattern. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- .../devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)