| Message ID | 20230114233500.3294789-3-lars@metafoo.de |
|---|---|
| State | Accepted |
| Commit | def70790be528439de137a238885125de953ab4d |
| Headers | show |
| Series | [1/3] clk: vc5: Use `clamp()` to restrict PLL range | expand |
Quoting Lars-Peter Clausen (2023-01-14 15:35:00) > The 5P49V60 clock generator is part of the same family of devices that is > described by the versaclock5 binding documentation. > > Add the compatible string of the 5P49V60 to the binding documentation. > > Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> > --- Applied to clk-next
diff --git a/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml b/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml index 61b246cf5e72..a2c6eea9871d 100644 --- a/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml +++ b/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml @@ -54,6 +54,7 @@ properties: - idt,5p49v5925 - idt,5p49v5933 - idt,5p49v5935 + - idt,5p49v60 - idt,5p49v6901 - idt,5p49v6965 - idt,5p49v6975
The 5P49V60 clock generator is part of the same family of devices that is described by the versaclock5 binding documentation. Add the compatible string of the 5P49V60 to the binding documentation. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> --- Documentation/devicetree/bindings/clock/idt,versaclock5.yaml | 1 + 1 file changed, 1 insertion(+)