From patchwork Tue Jan 10 17:56:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 641049 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B6DCDC678D9 for ; Tue, 10 Jan 2023 17:59:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233953AbjAJR54 (ORCPT ); Tue, 10 Jan 2023 12:57:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40444 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232558AbjAJR5Z (ORCPT ); Tue, 10 Jan 2023 12:57:25 -0500 Received: from mail-lf1-x129.google.com (mail-lf1-x129.google.com [IPv6:2a00:1450:4864:20::129]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D72A815723 for ; Tue, 10 Jan 2023 09:56:14 -0800 (PST) Received: by mail-lf1-x129.google.com with SMTP id v25so19657074lfe.12 for ; Tue, 10 Jan 2023 09:56:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=V2dTan/Kw4znHZMy+taD1K9hv7WX3VWk+z9jh04BKaU=; b=KJs3o86FAQHUCWODom2ShunZ4d54eR2HZqG+loTlcfBCWNUD7adM51iO2tsu5bBbBg KhNkEVlTMdn85Zu9CIDafIT4j7ZOPHrVZR3ULuXECcP7uTYIfDlYs7OX8g0I7tYHoXiC rkweUfq0WONZwg5LANvsUYh3QFITidK0Ev9f7OT1Ai5NGohX9zdKSYC/yLPF24wFNE/G 5aenIqbHwhFxE7QgHvFG4poZdpHy5a3PwzdituJoI8Pin74c4mTpJncleLzIUkzqG7NA 7rEVOwKADODqC3P6DDiXzs74VJ1XHx97MP+l9Zsd9Gqz9UdAy2xbSnCoFSv7kzvQE3wJ 1MsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=V2dTan/Kw4znHZMy+taD1K9hv7WX3VWk+z9jh04BKaU=; b=Up5jKcwkQ4u63r4NG2Csj6TbSUhEXUARI+tu610LCC2XG8Ee+VwNFVH8vZs45OryGy dw9m4Y2L//BlJC4gJAaIc4DmLNpyH9hNwLvto6SfgdxUV1aXMx2T7dAhg8Tiuv5k/mwl +/8uA9ks99a2vzSOcZFLX5+uB4BaFOt30Il+nISnL3Nya6h+hfRW0YjVIWsOQs0JOaem 6+vpD+eVUiX+p5GVGPB3o5BAg4Axz1+9c8LQTSorljcG1xWDGIMHYR4dkmYa/sID0Iui IaCTHS3rvrmEJFtwj7nTf3W2g2l6GPvN8RW3nYbZNribmpnCifdJYj2SoguEZOVJiz9c 7MSg== X-Gm-Message-State: AFqh2koWB+aiXWcOgppt6GwlraYGFqTt3EXOhHDLEkk2TRmQ5bmwCwJv f5FvLJvRo+g/YnMEgt37SmX9Gw== X-Google-Smtp-Source: AMrXdXslXMJbDYX0HzQL+JLarynNBVCpT0VT1nPeDZuFVwH4OHScH/Bl72AezVX4fCsTNtf1yvcGlQ== X-Received: by 2002:a05:6512:ea2:b0:4b5:5bcc:cbcd with SMTP id bi34-20020a0565120ea200b004b55bcccbcdmr20427226lfb.0.1673373372907; Tue, 10 Jan 2023 09:56:12 -0800 (PST) Received: from localhost.localdomain (abxi45.neoplus.adsl.tpnet.pl. [83.9.2.45]) by smtp.gmail.com with ESMTPSA id x9-20020a0565123f8900b004a1e104b269sm2275056lfa.34.2023.01.10.09.56.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jan 2023 09:56:12 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: marijn.suijten@somainline.org, angelogioacchino.delregno@collabora.com, Konrad Dybcio , AngeloGioacchino Del Regno , Rob Herring , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v8 1/5] dt-bindings: soc: qcom: cpr3: Add bindings for CPR3 driver Date: Tue, 10 Jan 2023 18:56:01 +0100 Message-Id: <20230110175605.1240188-2-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230110175605.1240188-1-konrad.dybcio@linaro.org> References: <20230110175605.1240188-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: AngeloGioacchino Del Regno Add the bindings for the CPR3 driver to the documentation. Reviewed-by: Rob Herring Signed-off-by: AngeloGioacchino Del Regno [Konrad: Add type reference to acc-syscon; update AGdR's email] Signed-off-by: Konrad Dybcio --- .../bindings/soc/qcom/qcom,cpr3.yaml | 242 ++++++++++++++++++ 1 file changed, 242 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml new file mode 100644 index 000000000000..52e87061a04b --- /dev/null +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml @@ -0,0 +1,242 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/soc/qcom/qcom,cpr3.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm Core Power Reduction v3/v4/Hardened (CPR3, CPR4, CPRh) + +description: | + CPR (Core Power Reduction) is a technology to reduce core power on a CPU + or other device. Each OPP of a device corresponds to a "corner" that has + a range of valid voltages for a particular frequency. While the device is + running at a particular frequency, CPR monitors dynamic factors such as + temperature, etc. and suggests or, in the CPR-Hardened case performs, + adjustments to the voltage to save power and meet silicon characteristic + requirements. + +maintainers: + - AngeloGioacchino Del Regno + +properties: + compatible: + oneOf: + - description: CPRv3 controller + items: + - const: qcom,cpr3 + - description: CPRv4 controller + items: + - const: qcom,cpr4 + - description: CPRv4-Hardened controller + items: + - enum: + - qcom,msm8998-cprh + - qcom,sdm630-cprh + - const: qcom,cprh + + reg: + description: Base address and size of the CPR controller(s) + minItems: 1 + maxItems: 2 + + interrupts: + maxItems: 1 + + clock-names: + items: + - const: "ref" + + clocks: + items: + - description: CPR reference clock + + vdd-supply: + description: Autonomous Phase Control (APC) or other power supply + + '#power-domain-cells': + const: 1 + + acc-syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to syscon for writing ACC settings + + nvmem-cells: + description: Cells containing the fuse corners and revision data + minItems: 10 + maxItems: 32 + + nvmem-cell-names: + minItems: 10 + maxItems: 32 + + operating-points-v2: true + +required: + - compatible + - reg + - clock-names + - clocks + - "#power-domain-cells" + - nvmem-cells + - nvmem-cell-names + - operating-points-v2 + +additionalProperties: false + +examples: + - | + #include + #include + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu@0 { + compatible = "qcom,kryo280"; + device_type = "cpu"; + reg = <0x0 0x0>; + operating-points-v2 = <&cpu_gold_opp_table>; + power-domains = <&apc_cprh 0>; + power-domain-names = "cprh"; + }; + + cpu@100 { + compatible = "qcom,kryo280"; + device_type = "cpu"; + reg = <0x0 0x0>; + operating-points-v2 = <&cpu_silver_opp_table>; + power-domains = <&apc_cprh 1>; + power-domain-names = "cprh"; + }; + }; + + cpu_gold_opp_table: opp-table-gold { + compatible = "operating-points-v2"; + opp-shared; + + opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + required-opps = <&cprh_opp3>; + }; + opp-1113600000 { + opp-hz = /bits/ 64 <1113600000>; + required-opps = <&cprh_opp2>; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&cprh_opp1>; + }; + }; + + cpu_silver_opp_table: opp-table-silver { + compatible = "operating-points-v2"; + opp-shared; + + opp-1843200000 { + opp-hz = /bits/ 64 <1843200000>; + required-opps = <&cprh_opp3>; + }; + opp-1094400000 { + opp-hz = /bits/ 64 <1094400000>; + required-opps = <&cprh_opp2>; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&cprh_opp1>; + }; + }; + + cprh_opp_table: opp-table-cprh { + compatible = "operating-points-v2-qcom-level"; + + cprh_opp1: opp1 { + opp-level = <1>; + qcom,opp-fuse-level = <1>; + }; + cprh_opp2: opp2 { + opp-level = <2>; + qcom,opp-fuse-level = <2>; + }; + cprh_opp3: opp3 { + opp-level = <3>; + qcom,opp-fuse-level = <2 3>; + }; + }; + + apc_cprh: power-controller@179c8000 { + compatible = "qcom,msm8998-cprh", "qcom,cprh"; + reg = <0x0179c8000 0x4000>, <0x0179c4000 0x4000>; + clocks = <&gcc GCC_HMSS_RBCPR_CLK>; + clock-names = "ref"; + + #power-domain-cells = <1>; + operating-points-v2 = <&cprh_opp_table>; + + nvmem-cells = <&cpr_efuse_speedbin>, + <&cpr_fuse_revision>, + <&cpr_quot0_pwrcl>, + <&cpr_quot1_pwrcl>, + <&cpr_quot2_pwrcl>, + <&cpr_quot3_pwrcl>, + <&cpr_quot_offset1_pwrcl>, + <&cpr_quot_offset2_pwrcl>, + <&cpr_quot_offset3_pwrcl>, + <&cpr_init_voltage0_pwrcl>, + <&cpr_init_voltage1_pwrcl>, + <&cpr_init_voltage2_pwrcl>, + <&cpr_init_voltage3_pwrcl>, + <&cpr_ro_sel0_pwrcl>, + <&cpr_ro_sel1_pwrcl>, + <&cpr_ro_sel2_pwrcl>, + <&cpr_ro_sel3_pwrcl>, + <&cpr_quot0_perfcl>, + <&cpr_quot1_perfcl>, + <&cpr_quot2_perfcl>, + <&cpr_quot3_perfcl>, + <&cpr_quot_offset1_perfcl>, + <&cpr_quot_offset2_perfcl>, + <&cpr_quot_offset3_perfcl>, + <&cpr_init_voltage0_perfcl>, + <&cpr_init_voltage1_perfcl>, + <&cpr_init_voltage2_perfcl>, + <&cpr_init_voltage3_perfcl>, + <&cpr_ro_sel0_perfcl>, + <&cpr_ro_sel1_perfcl>, + <&cpr_ro_sel2_perfcl>, + <&cpr_ro_sel3_perfcl>; + + nvmem-cell-names = "cpr_speed_bin", + "cpr_fuse_revision", + "cpr0_quotient1", + "cpr0_quotient2", + "cpr0_quotient3", + "cpr0_quotient4", + "cpr0_quotient_offset2", + "cpr0_quotient_offset3", + "cpr0_quotient_offset4", + "cpr0_init_voltage1", + "cpr0_init_voltage2", + "cpr0_init_voltage3", + "cpr0_init_voltage4", + "cpr0_ring_osc1", + "cpr0_ring_osc2", + "cpr0_ring_osc3", + "cpr0_ring_osc4", + "cpr1_quotient1", + "cpr1_quotient2", + "cpr1_quotient3", + "cpr1_quotient4", + "cpr1_quotient_offset2", + "cpr1_quotient_offset3", + "cpr1_quotient_offset4", + "cpr1_init_voltage1", + "cpr1_init_voltage2", + "cpr1_init_voltage3", + "cpr1_init_voltage4", + "cpr1_ring_osc1", + "cpr1_ring_osc2", + "cpr1_ring_osc3", + "cpr1_ring_osc4"; + }; +...