From patchwork Tue Jan 3 14:11:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 638874 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE64CC53210 for ; Tue, 3 Jan 2023 14:12:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237788AbjACOMB (ORCPT ); Tue, 3 Jan 2023 09:12:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58104 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237797AbjACOL3 (ORCPT ); Tue, 3 Jan 2023 09:11:29 -0500 Received: from mail-pj1-x1036.google.com (mail-pj1-x1036.google.com [IPv6:2607:f8b0:4864:20::1036]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 18C96E0F7 for ; Tue, 3 Jan 2023 06:11:29 -0800 (PST) Received: by mail-pj1-x1036.google.com with SMTP id 60-20020a17090a0fc200b002264ebad204so9586289pjz.1 for ; Tue, 03 Jan 2023 06:11:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bVqqR8oYcz8ddBS+TT8ZlpXaMsGagFVr9rYdfxP/rIg=; b=kW8IcmMw6snEgGMOnD3J92gTuk6kXiuNTjEsajrxn76hj89qmb0gT/j1/qFeeaZcTK J7LFnoEKURv0KZL/X29slpZTSrySPN5sRBqG+GbClcwUnXFtzoS6NbTHnUJ8vGga4irf 9lxRXfjRRUsTze6dbDeO3NxWQPkVIvEoltyCBU1H9fZNrbEqGBmVyV/XBJpp3FSgVUTH Yil5BTK+LuQ0bQZ80GE9sQ//XmF1G1yIs+uwTCzAZyhAXRaLkvK+gWt2lO/sVASuB8KD qTS7RFi9IQW6i5O1skxC9zShTpxzBKgZj+Y6P81xB5o6I+lZJxTCH2jgccHosXEmTglz TJPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bVqqR8oYcz8ddBS+TT8ZlpXaMsGagFVr9rYdfxP/rIg=; b=f9h7ZFefTrAJ21RiFD7XiBtyWff3vd7hT7HRHQ/Gi8Qya3UCxjd1sMfnHHWhA4OfGQ goseIDgNcuh5DUcq1WKVGoYd5Vnu6SiNj2GGFxbnGMfos/QNHnOH1tmAufv3bSq33N5H AqkYH+IhpRpy8xgKvcqU5L8ni7/5GyWMuInU9SAG2IqbRMWNduA0B6Q+woQyaQvlxHUI vESbNijQTn/b0jSjC7dI3YbBzow1oc+E8ES3ogLS8TOhneHTeejA951P9bnft3hnRdpO I4VWiBtDaLjTX1F5SEm6X+cJTYpaKkmkB+gZ86j/bUV+PWTnrql0EgLc4euSF+KiJEEb m2JQ== X-Gm-Message-State: AFqh2kqZ+i29exX7aAfQe1++iF4jzT0e7OX0QWHU4j3C8FUrabO9EdoJ RsizQy+lo6Cx5kHqsMnLHdP9YA== X-Google-Smtp-Source: AMrXdXvHiZ2mubjd6ktVYDES2Wzs1jni6FSXsvkL3Z/HXI4YqE6gXpPnnbII14HUfEZDsTFUbo5JNw== X-Received: by 2002:a17:902:7610:b0:192:751d:b2e4 with SMTP id k16-20020a170902761000b00192751db2e4mr28680533pll.48.1672755088680; Tue, 03 Jan 2023 06:11:28 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([171.76.85.241]) by smtp.gmail.com with ESMTPSA id l3-20020a170902e2c300b00192bf7eaf28sm6146117plc.286.2023.01.03.06.11.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Jan 2023 06:11:28 -0800 (PST) From: Anup Patel To: Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Paul Walmsley , Daniel Lezcano , Thomas Gleixner Cc: Andrew Jones , Atish Patra , Samuel Holland , Conor Dooley , Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel , Palmer Dabbelt Subject: [PATCH v6 3/3] clocksource: timer-riscv: Set CLOCK_EVT_FEAT_C3STOP based on DT Date: Tue, 3 Jan 2023 19:41:02 +0530 Message-Id: <20230103141102.772228-4-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230103141102.772228-1-apatel@ventanamicro.com> References: <20230103141102.772228-1-apatel@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org We should set CLOCK_EVT_FEAT_C3STOP for a clock_event_device only when riscv,timer-cannot-wake-cpu DT property is present in the RISC-V timer DT node. This way CLOCK_EVT_FEAT_C3STOP feature is set for clock_event_device based on RISC-V platform capabilities rather than having it set for all RISC-V platforms. Signed-off-by: Anup Patel Reviewed-by: Conor Dooley Acked-by: Palmer Dabbelt --- drivers/clocksource/timer-riscv.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c index a0d66fabf073..1b4b36df5484 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -28,6 +28,7 @@ #include static DEFINE_STATIC_KEY_FALSE(riscv_sstc_available); +static bool riscv_timer_cannot_wake_cpu; static int riscv_clock_next_event(unsigned long delta, struct clock_event_device *ce) @@ -85,6 +86,8 @@ static int riscv_timer_starting_cpu(unsigned int cpu) ce->cpumask = cpumask_of(cpu); ce->irq = riscv_clock_event_irq; + if (riscv_timer_cannot_wake_cpu) + ce->features |= CLOCK_EVT_FEAT_C3STOP; clockevents_config_and_register(ce, riscv_timebase, 100, 0x7fffffff); enable_percpu_irq(riscv_clock_event_irq, @@ -139,6 +142,13 @@ static int __init riscv_timer_init_dt(struct device_node *n) if (cpuid != smp_processor_id()) return 0; + child = of_find_compatible_node(NULL, NULL, "riscv,timer"); + if (child) { + riscv_timer_cannot_wake_cpu = of_property_read_bool(child, + "riscv,timer-cannot-wake-cpu"); + of_node_put(child); + } + domain = NULL; child = of_get_compatible_child(n, "riscv,cpu-intc"); if (!child) {