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[83.9.2.45]) by smtp.gmail.com with ESMTPSA id x11-20020a0565123f8b00b004b5adb59ed5sm4382143lfa.297.2023.01.02.01.47.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Jan 2023 01:47:01 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: marijn.suijten@somainline.org, Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 13/17] arm64: dts: qcom: sc7280: Pad addresses to 8 hex digits Date: Mon, 2 Jan 2023 10:46:38 +0100 Message-Id: <20230102094642.74254-14-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230102094642.74254-1-konrad.dybcio@linaro.org> References: <20230102094642.74254-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by: Konrad Dybcio --- v1 -> v2: No changes arch/arm64/boot/dts/qcom/sc7280.dtsi | 46 ++++++++++++++-------------- 1 file changed, 23 insertions(+), 23 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 0adf13399e64..cbf571baca9b 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2171,9 +2171,9 @@ ipa: ipa@1e40000 { iommus = <&apps_smmu 0x480 0x0>, <&apps_smmu 0x482 0x0>; - reg = <0 0x1e40000 0 0x8000>, - <0 0x1e50000 0 0x4ad0>, - <0 0x1e04000 0 0x23000>; + reg = <0 0x01e40000 0 0x8000>, + <0 0x01e50000 0 0x4ad0>, + <0 0x01e04000 0 0x23000>; reg-names = "ipa-reg", "ipa-shared", "gsi"; @@ -2455,7 +2455,7 @@ lpass_cpu: audio@3987000 { lpass_hm: clock-controller@3c00000 { compatible = "qcom,sc7280-lpasshm"; - reg = <0 0x3c00000 0 0x28>; + reg = <0 0x03c00000 0 0x28>; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "bi_tcxo"; #clock-cells = <1>; @@ -3489,7 +3489,7 @@ IPCC_MPROC_SIGNAL_GLINK_QMP pmu@9091000 { compatible = "qcom,sc7280-llcc-bwmon"; - reg = <0 0x9091000 0 0x1000>; + reg = <0 0x09091000 0 0x1000>; interrupts = ; @@ -3571,7 +3571,7 @@ dc_noc: interconnect@90e0000 { }; gem_noc: interconnect@9100000 { - reg = <0 0x9100000 0 0xe2200>; + reg = <0 0x09100000 0 0xe2200>; compatible = "qcom,sc7280-gem-noc"; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; @@ -3586,8 +3586,8 @@ system-cache-controller@9200000 { eud: eud@88e0000 { compatible = "qcom,sc7280-eud","qcom,eud"; - reg = <0 0x88e0000 0 0x2000>, - <0 0x88e2000 0 0x1000>; + reg = <0 0x088e0000 0 0x2000>, + <0 0x088e2000 0 0x1000>; interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>; ports { port@0 { @@ -3750,7 +3750,7 @@ opp-460000048 { videocc: clock-controller@aaf0000 { compatible = "qcom,sc7280-videocc"; - reg = <0 0xaaf0000 0 0x10000>; + reg = <0 0x0aaf0000 0 0x10000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>; clock-names = "bi_tcxo", "bi_tcxo_ao"; @@ -3773,7 +3773,7 @@ camcc: clock-controller@ad00000 { dispcc: clock-controller@af00000 { compatible = "qcom,sc7280-dispcc"; - reg = <0 0xaf00000 0 0x20000>; + reg = <0 0x0af00000 0 0x20000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_DISP_GPLL0_CLK_SRC>, <&mdss_dsi_phy 0>, @@ -4001,10 +4001,10 @@ mdss_edp: edp@aea0000 { pinctrl-names = "default"; pinctrl-0 = <&edp_hot_plug_det>; - reg = <0 0xaea0000 0 0x200>, - <0 0xaea0200 0 0x200>, - <0 0xaea0400 0 0xc00>, - <0 0xaea1000 0 0x400>; + reg = <0 0x0aea0000 0 0x200>, + <0 0x0aea0200 0 0x200>, + <0 0x0aea0400 0 0xc00>, + <0 0x0aea1000 0 0x400>; interrupt-parent = <&mdss>; interrupts = <14>; @@ -4076,10 +4076,10 @@ opp-810000000 { mdss_edp_phy: phy@aec2a00 { compatible = "qcom,sc7280-edp-phy"; - reg = <0 0xaec2a00 0 0x19c>, - <0 0xaec2200 0 0xa0>, - <0 0xaec2600 0 0xa0>, - <0 0xaec2000 0 0x1c0>; + reg = <0 0x0aec2a00 0 0x19c>, + <0 0x0aec2200 0 0xa0>, + <0 0x0aec2600 0 0xa0>, + <0 0x0aec2000 0 0x1c0>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_EDP_CLKREF_EN>; @@ -4095,11 +4095,11 @@ mdss_edp_phy: phy@aec2a00 { mdss_dp: displayport-controller@ae90000 { compatible = "qcom,sc7280-dp"; - reg = <0 0xae90000 0 0x200>, - <0 0xae90200 0 0x200>, - <0 0xae90400 0 0xc00>, - <0 0xae91000 0 0x400>, - <0 0xae91400 0 0x400>; + reg = <0 0x0ae90000 0 0x200>, + <0 0x0ae90200 0 0x200>, + <0 0x0ae90400 0 0xc00>, + <0 0x0ae91000 0 0x400>, + <0 0x0ae91400 0 0x400>; interrupt-parent = <&mdss>; interrupts = <12>;