From patchwork Tue Dec 27 12:22:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Qiu X-Patchwork-Id: 637113 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AF838C4167B for ; Tue, 27 Dec 2022 12:25:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231557AbiL0MZM convert rfc822-to-8bit (ORCPT ); Tue, 27 Dec 2022 07:25:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36886 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232380AbiL0MYV (ORCPT ); Tue, 27 Dec 2022 07:24:21 -0500 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6DE83112D; Tue, 27 Dec 2022 04:22:33 -0800 (PST) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 5AB9724E00A; Tue, 27 Dec 2022 20:22:31 +0800 (CST) Received: from EXMBX168.cuchost.com (172.16.6.78) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 27 Dec 2022 20:22:31 +0800 Received: from williamqiu-virtual-machine.starfivetech.com (171.223.208.138) by EXMBX168.cuchost.com (172.16.6.78) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 27 Dec 2022 20:22:30 +0800 From: William Qiu To: , , CC: Rob Herring , Krzysztof Kozlowski , Jaehoon Chung , Ulf Hansson , William Qiu , Subject: [PATCH v2 3/3] riscv: dts: starfive: Add mmc node Date: Tue, 27 Dec 2022 20:22:27 +0800 Message-ID: <20221227122227.460921-4-william.qiu@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221227122227.460921-1-william.qiu@starfivetech.com> References: <20221227122227.460921-1-william.qiu@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX168.cuchost.com (172.16.6.78) X-YovoleRuleAgent: yovoleflag Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds the mmc node for the StarFive JH7110 SoC. Set sdioo node to emmc and set sdio1 node to sd. Signed-off-by: William Qiu --- .../jh7110-starfive-visionfive-v2.dts | 25 ++++++++++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 38 +++++++++++++++++++ 2 files changed, 63 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts index c8946cf3a268..d8244fd1f5a0 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts @@ -47,6 +47,31 @@ &clk_rtc { clock-frequency = <32768>; }; +&mmc0 { + max-frequency = <100000000>; + card-detect-delay = <300>; + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; + cap-mmc-hw-reset; + post-power-on-delay-ms = <200>; + status = "okay"; +}; + +&mmc1 { + max-frequency = <100000000>; + card-detect-delay = <300>; + bus-width = <4>; + no-sdio; + no-mmc; + broken-cd; + cap-sd-highspeed; + post-power-on-delay-ms = <200>; + status = "okay"; +}; + &gmac0_rmii_refin { clock-frequency = <50000000>; }; diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index c22e8f1d2640..08a780d2c0f4 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -331,6 +331,11 @@ aoncrg: clock-controller@17000000 { #reset-cells = <1>; }; + syscon: syscon@13030000 { + compatible = "starfive,syscon", "syscon"; + reg = <0x0 0x13030000 0x0 0x1000>; + }; + gpio: gpio@13040000 { compatible = "starfive,jh7110-sys-pinctrl"; reg = <0x0 0x13040000 0x0 0x10000>; @@ -433,5 +438,38 @@ uart5: serial@12020000 { reg-shift = <2>; status = "disabled"; }; + + /* unremovable emmc as mmcblk0 */ + mmc0: mmc@16010000 { + compatible = "starfive,jh7110-mmc"; + reg = <0x0 0x16010000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>, + <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>; + clock-names = "biu","ciu"; + resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>; + reset-names = "reset"; + interrupts = <74>; + fifo-depth = <32>; + fifo-watermark-aligned; + data-addr = <0>; + starfive,syscon = <&syscon 0x14 0x1a 0x7c000000>; + status = "disabled"; + }; + + mmc1: mmc@16020000 { + compatible = "starfive,jh7110-mmc"; + reg = <0x0 0x16020000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_SDIO1_AHB>, + <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>; + clock-names = "biu","ciu"; + resets = <&syscrg JH7110_SYSRST_SDIO1_AHB>; + reset-names = "reset"; + interrupts = <75>; + fifo-depth = <32>; + fifo-watermark-aligned; + data-addr = <0>; + starfive,syscon = <&syscon 0x9c 0x1 0x3e>; + status = "disabled"; + }; }; };