From patchwork Mon Dec 26 22:49:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Acayan X-Patchwork-Id: 636862 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D819EC4708E for ; Mon, 26 Dec 2022 22:50:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232498AbiLZWuV (ORCPT ); Mon, 26 Dec 2022 17:50:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48024 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232433AbiLZWuC (ORCPT ); Mon, 26 Dec 2022 17:50:02 -0500 Received: from mail-il1-x129.google.com (mail-il1-x129.google.com [IPv6:2607:f8b0:4864:20::129]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1B3DF25E7; Mon, 26 Dec 2022 14:50:01 -0800 (PST) Received: by mail-il1-x129.google.com with SMTP id o13so6049255ilc.7; Mon, 26 Dec 2022 14:50:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zQtc0XYFcinmJ8ut/fhiEKUZ5qeGkZJwZ2bSsqd62BA=; b=HnmC8189q+Fa9iTc9WdQSuCmoD3ft+rlvNX0tvoaxddna5UeJ9KxSrQMa8lQKGAqpm eKZBWPCOAbszl2V2zwuffgzM7+A1tFDsoXWp4XsneEubRpjmlCnugK1tFKrSLdyFc4u3 S1GSRS/GMngf01Y5xvc2ZI4hcivJX3jkthEAHZ7klhNd6r8mZaRBWyAGB9YRN7ZzBOF4 E7Cfksn/7ZcNTiPgFf6P+UdoULi0YPIyYT59q72cL064K0BQS9MybdQRAhoIwrPt70f7 EYr7h1ybkzPwDp8+q/p6Qxw8VEGK9CaIvIXFnNK4IcJJw5vX4IGGU6CO/KKm7lTbgJC7 mDuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zQtc0XYFcinmJ8ut/fhiEKUZ5qeGkZJwZ2bSsqd62BA=; b=RrXwD1YmeqV7wcj0QHND5N1rDZah8GNls4wc/pu0bQyS1K0Afc6xRtDHyGdseGxSGt tdKwOUkpNX20TsmEpM1rRiJzYRyV3nvNh5EAu6uoRaiOVmUiqAN/qpJGag++J/5MF36e +4UV/MkqRTo3MmFAEgFr2QMbQYDNtme9N2YLgwzOx08j/W0sfjM9QYGtMcVl4zGGuBJk p4SroEF8yzrsMU+yTdusGBJxBIdH54cmgABrlCB1r7rIbt+LXz56yGLhvQ0ElhGdnBrY 3ziH712tK3X4iYhzUJL5d1WVms/fC9tHxboOd9eiHkpNByK67cwE45sFLoEZMRZw9lDz TiwA== X-Gm-Message-State: AFqh2krenTRCZcB+9l1BYj+rdZObATRozRobnsbWRIcUD+RbhmrOi0j+ zwo6ilwkA8JfOSKmtBqyw4A= X-Google-Smtp-Source: AMrXdXusiLnMoLTf2dq5BsvLFznZMZjOTWFjnS+kPUj90XehpeHn3pjfD7+DIgCz8ix1nafGDGCWng== X-Received: by 2002:a92:a806:0:b0:30b:ecf9:82f5 with SMTP id o6-20020a92a806000000b0030becf982f5mr7579719ilh.30.1672095000398; Mon, 26 Dec 2022 14:50:00 -0800 (PST) Received: from localhost ([2607:fea8:a2df:3d00::e694]) by smtp.gmail.com with ESMTPSA id m30-20020a02a15e000000b0037508cc0bc2sm3700707jah.12.2022.12.26.14.49.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Dec 2022 14:50:00 -0800 (PST) From: Richard Acayan To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org Cc: Odelu Kukatla , Luca Weiss , Richard Acayan Subject: [PATCH 1/4] dt-bindings: interconnect: add sdm670 interconnects Date: Mon, 26 Dec 2022 17:49:41 -0500 Message-Id: <20221226224944.37242-2-mailingradian@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221226224944.37242-1-mailingradian@gmail.com> References: <20221226224944.37242-1-mailingradian@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org There are controllable interconnects on Snapdragon 670. Add the compatible strings to the documentation and interconnect ID definitions. The device tree header was generated by linux-interconnect-driver-generator and the copyright year was changed. Signed-off-by: Richard Acayan --- .../bindings/interconnect/qcom,rpmh.yaml | 8 ++ .../dt-bindings/interconnect/qcom,sdm670.h | 136 ++++++++++++++++++ 2 files changed, 144 insertions(+) create mode 100644 include/dt-bindings/interconnect/qcom,sdm670.h diff --git a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml index a429a1ed1006..db1e93583554 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml @@ -75,6 +75,14 @@ properties: - qcom,sc8280xp-nspa-noc - qcom,sc8280xp-nspb-noc - qcom,sc8280xp-system-noc + - qcom,sdm670-aggre1-noc + - qcom,sdm670-aggre2-noc + - qcom,sdm670-config-noc + - qcom,sdm670-dc-noc + - qcom,sdm670-gladiator-noc + - qcom,sdm670-mem-noc + - qcom,sdm670-mmss-noc + - qcom,sdm670-system-noc - qcom,sdm845-aggre1-noc - qcom,sdm845-aggre2-noc - qcom,sdm845-config-noc diff --git a/include/dt-bindings/interconnect/qcom,sdm670.h b/include/dt-bindings/interconnect/qcom,sdm670.h new file mode 100644 index 000000000000..d26dedb9deb7 --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,sdm670.h @@ -0,0 +1,136 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ +/* + * Qualcomm SDM670 interconnect IDs + * + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SDM670_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_SDM670_H + +#define MASTER_A1NOC_CFG 0 +#define MASTER_BLSP_1 1 +#define MASTER_TSIF 2 +#define MASTER_EMMC 3 +#define MASTER_SDCC_2 4 +#define MASTER_SDCC_4 5 +#define MASTER_UFS_MEM 6 +#define SLAVE_A1NOC_SNOC 7 +#define SLAVE_SERVICE_A1NOC 8 + +#define MASTER_A2NOC_CFG 0 +#define MASTER_QDSS_BAM 1 +#define MASTER_BLSP_2 2 +#define MASTER_CNOC_A2NOC 3 +#define MASTER_CRYPTO_CORE_0 4 +#define MASTER_IPA 5 +#define MASTER_QDSS_ETR 6 +#define MASTER_USB3 7 +#define SLAVE_A2NOC_SNOC 8 +#define SLAVE_SERVICE_A2NOC 9 + + +#define MASTER_SPDM 0 +#define MASTER_SNOC_CNOC 1 +#define SLAVE_A1NOC_CFG 2 +#define SLAVE_A2NOC_CFG 3 +#define SLAVE_AOP 4 +#define SLAVE_AOSS 5 +#define SLAVE_CAMERA_CFG 6 +#define SLAVE_CLK_CTL 7 +#define SLAVE_CDSP_CFG 8 +#define SLAVE_RBCPR_CX_CFG 9 +#define SLAVE_CRYPTO_0_CFG 10 +#define SLAVE_DCC_CFG 11 +#define SLAVE_CNOC_DDRSS 12 +#define SLAVE_DISPLAY_CFG 13 +#define SLAVE_EMMC_CFG 14 +#define SLAVE_GLM 15 +#define SLAVE_GRAPHICS_3D_CFG 16 +#define SLAVE_IMEM_CFG 17 +#define SLAVE_IPA_CFG 18 +#define SLAVE_CNOC_MNOC_CFG 19 +#define SLAVE_PDM 20 +#define SLAVE_SOUTH_PHY_CFG 21 +#define SLAVE_PIMEM_CFG 22 +#define SLAVE_PRNG 23 +#define SLAVE_QDSS_CFG 24 +#define SLAVE_BLSP_2 25 +#define SLAVE_BLSP_1 26 +#define SLAVE_SDCC_2 27 +#define SLAVE_SDCC_4 28 +#define SLAVE_SNOC_CFG 29 +#define SLAVE_SPDM_WRAPPER 30 +#define SLAVE_TCSR 31 +#define SLAVE_TLMM_NORTH 32 +#define SLAVE_TLMM_SOUTH 33 +#define SLAVE_TSIF 34 +#define SLAVE_UFS_MEM_CFG 35 +#define SLAVE_USB3 36 +#define SLAVE_VENUS_CFG 37 +#define SLAVE_VSENSE_CTRL_CFG 38 +#define SLAVE_CNOC_A2NOC 39 +#define SLAVE_SERVICE_CNOC 40 + +#define MASTER_CNOC_DC_NOC 0 +#define SLAVE_LLCC_CFG 1 +#define SLAVE_MEM_NOC_CFG 2 + +#define MASTER_AMPSS_M0 0 +#define MASTER_GNOC_CFG 1 +#define SLAVE_GNOC_SNOC 2 +#define SLAVE_GNOC_MEM_NOC 3 +#define SLAVE_SERVICE_GNOC 4 + +#define MASTER_TCU_0 0 +#define MASTER_MEM_NOC_CFG 1 +#define MASTER_GNOC_MEM_NOC 2 +#define MASTER_MNOC_HF_MEM_NOC 3 +#define MASTER_MNOC_SF_MEM_NOC 4 +#define MASTER_SNOC_GC_MEM_NOC 5 +#define MASTER_SNOC_SF_MEM_NOC 6 +#define MASTER_GRAPHICS_3D 7 +#define SLAVE_MSS_PROC_MS_MPU_CFG 8 +#define SLAVE_MEM_NOC_GNOC 9 +#define SLAVE_LLCC 10 +#define SLAVE_MEM_NOC_SNOC 11 +#define SLAVE_SERVICE_MEM_NOC 12 +#define MASTER_LLCC 13 +#define SLAVE_EBI_CH0 14 + +#define MASTER_CNOC_MNOC_CFG 0 +#define MASTER_CAMNOC_HF0 1 +#define MASTER_CAMNOC_HF1 2 +#define MASTER_CAMNOC_SF 3 +#define MASTER_MDP_PORT0 4 +#define MASTER_MDP_PORT1 5 +#define MASTER_ROTATOR 6 +#define MASTER_VIDEO_P0 7 +#define MASTER_VIDEO_P1 8 +#define MASTER_VIDEO_PROC 9 +#define SLAVE_MNOC_SF_MEM_NOC 10 +#define SLAVE_MNOC_HF_MEM_NOC 11 +#define SLAVE_SERVICE_MNOC 12 + +#define MASTER_SNOC_CFG 0 +#define MASTER_A1NOC_SNOC 1 +#define MASTER_A2NOC_SNOC 2 +#define MASTER_GNOC_SNOC 3 +#define MASTER_MEM_NOC_SNOC 4 +#define MASTER_PIMEM 5 +#define MASTER_GIC 6 +#define SLAVE_APPSS 7 +#define SLAVE_SNOC_CNOC 8 +#define SLAVE_SNOC_MEM_NOC_GC 9 +#define SLAVE_SNOC_MEM_NOC_SF 10 +#define SLAVE_OCIMEM 11 +#define SLAVE_PIMEM 12 +#define SLAVE_SERVICE_SNOC 13 +#define SLAVE_QDSS_STM 14 +#define SLAVE_TCU 15 +#define MASTER_CAMNOC_HF0_UNCOMP 16 +#define MASTER_CAMNOC_HF1_UNCOMP 17 +#define MASTER_CAMNOC_SF_UNCOMP 18 +#define SLAVE_CAMNOC_UNCOMP 19 + +#endif