From patchwork Thu Dec 8 06:40:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sibi Sankar X-Patchwork-Id: 632621 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58AE7C63709 for ; Thu, 8 Dec 2022 06:41:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229564AbiLHGlF (ORCPT ); Thu, 8 Dec 2022 01:41:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45062 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229873AbiLHGlD (ORCPT ); Thu, 8 Dec 2022 01:41:03 -0500 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 583445C74A; Wed, 7 Dec 2022 22:41:02 -0800 (PST) Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2B84W2JD026651; Thu, 8 Dec 2022 06:40:56 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=EV3VPVNYaf/rR2f2F0SGWkrLynSHfwdvN3xUQYhwmBw=; b=BGGdpkYEOcATWy0MWVen6oiq7+fbjCQC9kGjk5Sjk5787gkwrNnGg4oNof6apkLmWR/E LLW+JxWqgHEkYRNujQRSLgaGLkO8cGSyhoDYlG12VEi2RAmK+g2GEm5sJeaGwr2IKHsa LxQVhwbfPXDODHEkFLgPa1Sq7fWzMLRSk6YsyW8e5VvCl4W/a7BfH1aVgkjcN/6Ygpn6 8Ik3XV+2aH8DQW5qLgmZ/SMCfnYPHUzYNe147GZKoMyI7dc6hE6CVsFMWGTdph25Rty/ tNrYtEnPrIJANlt7K+wNxXyhaA6wt2sZVXIWXU8u4A8PSObg4CWKBjLd02kb0J88JEE6 xw== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3macsyvb3h-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 08 Dec 2022 06:40:56 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 2B86etAW025374 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 8 Dec 2022 06:40:55 GMT Received: from blr-ubuntu-87.ap.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Wed, 7 Dec 2022 22:40:51 -0800 From: Sibi Sankar To: , CC: , , , , , , , , , Sibi Sankar Subject: [PATCH V6 1/2] dt-bindings: firmware: qcom,scm: Add optional interrupt Date: Thu, 8 Dec 2022 12:10:30 +0530 Message-ID: <20221208064031.2875-2-quic_sibis@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221208064031.2875-1-quic_sibis@quicinc.com> References: <20221208064031.2875-1-quic_sibis@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: q3EOiSkjlPPg5nrvcSlMSn0qpLpygHvR X-Proofpoint-ORIG-GUID: q3EOiSkjlPPg5nrvcSlMSn0qpLpygHvR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-08_04,2022-12-07_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 mlxscore=0 suspectscore=0 bulkscore=0 spamscore=0 mlxlogscore=999 priorityscore=1501 phishscore=0 clxscore=1015 adultscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2210170000 definitions=main-2212080055 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Guru Das Srinagesh Add an interrupt specification to the bindings to support the wait-queue feature on SM8450 SoCs. Signed-off-by: Guru Das Srinagesh Signed-off-by: Sibi Sankar --- The interrupt property for scm firmware from a binding perspective is completely optional i.e. not all tz fw running in the wild on sm8450 devices support this feature. The bootloader does the interrupt property addition on sm8450 devices with wait-queue support. v6: - Fix subject of bindings [Krzysztof] - Update commit message to include the SoC supporting the feature [Krzysztof] - Make the interrupt property valid on SM8450 SoC [Krzysztof] - Rebased on Krzysztof's narrow clocks and interconnect series. - Drop R-b v5: - Pick up R-b v4: - Qualify bindings [Krzysztoff] .../devicetree/bindings/firmware/qcom,scm.yaml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml index 8e6e9ebb343d..01c861f36983 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -73,6 +73,12 @@ properties: '#reset-cells': const: 1 + interrupts: + description: + The wait-queue interrupt that firmware raises as part of handshake + protocol to handle sleeping SCM calls. + maxItems: 1 + qcom,dload-mode: $ref: /schemas/types.yaml#/definitions/phandle-array items: @@ -162,6 +168,18 @@ allOf: properties: interconnects: false + # Interrupts + - if: + not: + properties: + compatible: + contains: + enum: + - qcom,scm-sm8450 + then: + properties: + interrupts: false + required: - compatible